From patchwork Tue Apr 8 17:47:43 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Todd Previte X-Patchwork-Id: 3950211 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 4E007BFF02 for ; Tue, 8 Apr 2014 17:48:22 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 86738203AC for ; Tue, 8 Apr 2014 17:48:21 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id ABDE4203B5 for ; Tue, 8 Apr 2014 17:48:20 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 487B96E499; Tue, 8 Apr 2014 10:48:20 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-pb0-f41.google.com (mail-pb0-f41.google.com [209.85.160.41]) by gabe.freedesktop.org (Postfix) with ESMTP id A2A7C6E4B4 for ; Tue, 8 Apr 2014 10:48:18 -0700 (PDT) Received: by mail-pb0-f41.google.com with SMTP id jt11so1359757pbb.28 for ; Tue, 08 Apr 2014 10:48:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=zaGQsIfAvQ2X+vJJS0H7XeOgNHZYCJW0MixMh3nMoYw=; b=RiagZ7T9fV04/N/oANIPFgmUUzTKmruyxQoI3XGmYt+Ea2myGrnsNedG0nn5Q9rWwL bbvPeXuBCyBRZwHmDZZ0HJjCng4aHiZQwbi1dpOF+yD5hl8W6J/n6eh4AWJhWE0E7MFd AwMoNsN4B2OgW8HLBHhhvQycI3ZmEeVCfAw+XNL8DXyDS15MkRnoabBU8onnisd79iro HXRqSGzKlN3Be5wcNGrbuAOooP1o9Amoqe/EMY/AUq5YQhlXFYO62K7v8Tz+KtFmRX+Y eKLr5zHCBYzu+6mA+I3COmqamnA2FHY8QbG9BloHZSOC5X3CCMOSCy6p+HgRJr3ckgfq KT8Q== X-Received: by 10.66.162.74 with SMTP id xy10mr6341829pab.4.1396979298530; Tue, 08 Apr 2014 10:48:18 -0700 (PDT) Received: from localhost.localdomain (ip72-201-95-47.ph.ph.cox.net. [72.201.95.47]) by mx.google.com with ESMTPSA id e6sm5973219pbg.4.2014.04.08.10.48.15 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Tue, 08 Apr 2014 10:48:16 -0700 (PDT) From: Todd Previte To: intel-gfx@lists.freedesktop.org Date: Tue, 8 Apr 2014 10:47:43 -0700 Message-Id: <1396979263-3245-6-git-send-email-tprevite@gmail.com> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1396979263-3245-1-git-send-email-tprevite@gmail.com> References: <1396979263-3245-1-git-send-email-tprevite@gmail.com> Subject: [Intel-gfx] [PATCH 5/5] drm/i915: Displayport - Add function to execute a single iteration of channel equalization X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, T_DKIM_INVALID, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Adds a function to execute a single iteration of the channel equalization sequence for Displayport. This is functionality required to establish more fine-grained control over the Displayport interface, both for operational reliability and compliance testing. Signed-off-by: Todd Previte --- drivers/gpu/drm/i915/intel_dp.c | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 6baa26c..66dbda6 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -2878,6 +2878,37 @@ exit: return clock_recovery_status; } +uint32_t intel_dp_exec_channel_equalization(struct intel_dp *intel_dp) +{ + uint32_t channel_equalization_status = DP_CHANNEL_EQUALIZATION_FAILED; + uint8_t link_status[DP_LINK_STATUS_SIZE]; + + // Set the correct training pattern + if (intel_dp->dpcd[DP_DPCD_REV] >= 0x12) + intel_dp_set_training_pattern(DP_TRAINING_PATTERN_2, intel_dp); + else + intel_dp_set_training_pattern(DP_TRAINING_PATTERN_2, intel_dp); + + // Wait for channel equalization time period to expire + drm_dp_link_train_channel_eq_delay(intel_dp->dpcd); + + // Check link status + if (!intel_dp_get_link_status(intel_dp, link_status)) { + channel_equalization_status = DP_LINK_STATUS_READ_FAILED; + goto exit; + } + + // Verify that both CR is still valid and CE is successful + if (intel_dp_verify_link_status(DP_LINK_TRAINING_STATE_CLOCK_REC, + intel_dp->lane_count, link_status) && + intel_dp_verify_link_status(DP_LINK_TRAINING_STATE_CHANNEL_EQ, + intel_dp->lane_count, link_status)) + channel_equalization_status = DP_CHANNEL_EQUALIZATION_COMPLETE; + +exit: + return channel_equalization_status; +} + static void intel_dp_link_down(struct intel_dp *intel_dp) {