From patchwork Fri Apr 11 17:00:16 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jesse Barnes X-Patchwork-Id: 3971321 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 3B722BFF02 for ; Fri, 11 Apr 2014 16:59:00 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 6240A20494 for ; Fri, 11 Apr 2014 16:58:59 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 7AE3220465 for ; Fri, 11 Apr 2014 16:58:58 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 054096E403; Fri, 11 Apr 2014 09:58:58 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from gproxy3-pub.mail.unifiedlayer.com (gproxy3-pub.mail.unifiedlayer.com [69.89.30.42]) by gabe.freedesktop.org (Postfix) with SMTP id 20FC26E403 for ; Fri, 11 Apr 2014 09:58:56 -0700 (PDT) Received: (qmail 30121 invoked by uid 0); 11 Apr 2014 16:58:55 -0000 Received: from unknown (HELO CMOut01) (10.0.90.82) by gproxy3.mail.unifiedlayer.com with SMTP; 11 Apr 2014 16:58:55 -0000 Received: from box514.bluehost.com ([74.220.219.114]) by CMOut01 with id ogyq1n00P2UhLwi01gytMY; Fri, 11 Apr 2014 10:58:54 -0600 X-Authority-Analysis: v=2.1 cv=ZpR+dbLG c=1 sm=1 tr=0 a=9W6Fsu4pMcyimqnCr1W0/w==:117 a=9W6Fsu4pMcyimqnCr1W0/w==:17 a=cNaOj0WVAAAA:8 a=f5113yIGAAAA:8 a=vPYY4gcTGxkA:10 a=3ROhxo7VqVMA:10 a=TBVoxVdAAAAA:8 a=QyXUC8HyAAAA:8 a=GhZ5P8ky69gA:10 a=noBwr2J6l1kA:10 a=X49T-rV6pwAdw6dUPG0A:9 a=rW6DTWptwo0A:10 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=virtuousgeek.org; s=default; h=Message-Id:Date:Subject:To:From; bh=tquc9Mlxna996gLp5CuCTrAgqg2haNgS1WzVYLMuT6s=; b=FOlfRiAqdQM+pf1rLm+68YMqBw2a71DVVgUdB8VMDAKlrvBERdJ9iDyJ3mGS2Lk9uEXTAIDo0RGbG/Nf62XA0WTfH6CofMH/xiBEKzCPjxNHlh7OP5KKvv4Vbj/rOWxq; Received: from [67.161.37.189] (port=58473 helo=jbarnes-desktop.intel.com) by box514.bluehost.com with esmtpsa (TLSv1.1:DHE-RSA-AES256-SHA:256) (Exim 4.82) (envelope-from ) id 1WYemw-0006mC-P2 for intel-gfx@lists.freedesktop.org; Fri, 11 Apr 2014 10:58:50 -0600 From: Jesse Barnes To: intel-gfx@lists.freedesktop.org Date: Fri, 11 Apr 2014 10:00:16 -0700 Message-Id: <1397235616-25925-1-git-send-email-jbarnes@virtuousgeek.org> X-Mailer: git-send-email 1.7.9.5 X-Identified-User: {10642:box514.bluehost.com:virtuous:virtuousgeek.org} {sentby:smtp auth 67.161.37.189 authed with jbarnes@virtuousgeek.org} Subject: [Intel-gfx] [PATCH] drm/i915/vlv: assert and de-assert sideband reset on resume X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.5 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED,RP_MATCHES_RCVD,T_DKIM_INVALID,UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This is a bit like the CMN reset de-assert we do in DPIO_CTL, except that it resets the whole common lane section of the PHY. This is required on machines where the BIOS doesn't do this for us on resume to properly re-calibrate and get the PHY ready to transmit data. Without this patch, such machines won't resume correctly much of the time, with the symptom being a 'port ready' timeout and/or a link training failure. I'm open to better suggestions on how to do the power well toggle, with the existing code it looks like I'd have to walk through a bunch of power domains looking for a match, then call a generic function which will warn. I'd prefer to just expose the specific domains directly for low level platform code like this. Signed-off-by: Jesse Barnes --- drivers/gpu/drm/i915/intel_pm.c | 4 ++-- drivers/gpu/drm/i915/intel_uncore.c | 19 +++++++++++++++++++ 2 files changed, 21 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index fa00185..3afd0bc 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -5454,8 +5454,8 @@ static bool i9xx_always_on_power_well_enabled(struct drm_i915_private *dev_priv, return true; } -static void vlv_set_power_well(struct drm_i915_private *dev_priv, - struct i915_power_well *power_well, bool enable) +void vlv_set_power_well(struct drm_i915_private *dev_priv, + struct i915_power_well *power_well, bool enable) { enum punit_power_well power_well_id = power_well->data; u32 mask; diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c index 2a72bab..f1abd2d 100644 --- a/drivers/gpu/drm/i915/intel_uncore.c +++ b/drivers/gpu/drm/i915/intel_uncore.c @@ -363,6 +363,9 @@ static void intel_uncore_forcewake_reset(struct drm_device *dev, bool restore) spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); } +void vlv_set_power_well(struct drm_i915_private *dev_priv, + struct i915_power_well *power_well, bool enable); + void intel_uncore_early_sanitize(struct drm_device *dev) { struct drm_i915_private *dev_priv = dev->dev_private; @@ -381,6 +384,22 @@ void intel_uncore_early_sanitize(struct drm_device *dev) DRM_INFO("Found %zuMB of eLLC\n", dev_priv->ellc_size); } + /* + * From VLV2A0_DP_eDP_HDMI_DPIO_driver_vbios_notes_11.docx: + * Need to assert and de-assert PHY SB reset by gating the common + * lane power, then un-gating it. + * Simply ungating isn't enough to reset the PHY enough to get + * ports and lanes running. + */ + if (IS_VALLEYVIEW(dev)) { + struct i915_power_well cmn_well = { + .data = PUNIT_POWER_WELL_DPIO_CMN_BC + }; + + vlv_set_power_well(dev_priv, &cmn_well, false); + vlv_set_power_well(dev_priv, &cmn_well, true); + } + /* clear out old GT FIFO errors */ if (IS_GEN6(dev) || IS_GEN7(dev)) __raw_i915_write32(dev_priv, GTFIFODBG,