From patchwork Mon Apr 14 09:45:25 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: sourab.gupta@intel.com X-Patchwork-Id: 3979041 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 1DEA7BFF02 for ; Mon, 14 Apr 2014 09:44:49 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 2C3AE2018E for ; Mon, 14 Apr 2014 09:44:48 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 3EE762017B for ; Mon, 14 Apr 2014 09:44:47 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id BA97A6E74D; Mon, 14 Apr 2014 02:44:46 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTP id 60BE26E74D for ; Mon, 14 Apr 2014 02:44:45 -0700 (PDT) Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga101.jf.intel.com with ESMTP; 14 Apr 2014 02:44:45 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="4.97,856,1389772800"; d="scan'208";a="492493617" Received: from sourabgu-desktop.iind.intel.com ([10.223.82.69]) by orsmga001.jf.intel.com with ESMTP; 14 Apr 2014 02:44:42 -0700 From: sourab.gupta@intel.com To: intel-gfx@lists.freedesktop.org Date: Mon, 14 Apr 2014 15:15:25 +0530 Message-Id: <1397468725-9520-1-git-send-email-sourab.gupta@intel.com> X-Mailer: git-send-email 1.8.5.1 In-Reply-To: <1396932146.19246.5.camel@sourabgu-desktop> References: <1396932146.19246.5.camel@sourabgu-desktop> Cc: Daniel Vetter , Akash Goel , Sourab Gupta Subject: [Intel-gfx] [PATCH v5 2/6] drm/i915/vlv: Added a rendering specific Hw WA 'WaSendDummy3dPrimitveAfterSetContext' X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-5.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Akash Goel This workaround is needed on VLV for the HW context feature. It is used after adding the mi_set_context command in ring buffer for Hw context switch. As per the spec "The software must send a pipe_control with a CS stall and a post sync operation and then a dummy DRAW after every MI_SET_CONTEXT and after any PIPELINE_SELECT that is enabling 3D mode". Tested only for vlv. v2: Modified the WA comment. (Ville) v3: Added the vlv identifier with the WA name v4: Check removed for scratch page initialization. (Chris/Daniel) v5: Refactored based on latest codebase. Also WA added for full Gen7. Signed-off-by: Sourab Gupta Signed-off-by: Akash Goel --- drivers/gpu/drm/i915/i915_gem_context.c | 55 +++++++++++++++++++++++++++++++-- drivers/gpu/drm/i915/i915_reg.h | 1 + drivers/gpu/drm/i915/intel_ringbuffer.c | 9 ++++++ drivers/gpu/drm/i915/intel_ringbuffer.h | 1 + 4 files changed, 64 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c index f77b4c1..b6d2a67 100644 --- a/drivers/gpu/drm/i915/i915_gem_context.c +++ b/drivers/gpu/drm/i915/i915_gem_context.c @@ -545,6 +545,47 @@ i915_gem_context_get(struct drm_i915_file_private *file_priv, u32 id) return ctx; } +static inline void +mi_set_context_dummy3d_prim_wa(struct intel_ring_buffer *ring) +{ + u32 scratch_addr; + u32 flags = 0; + + /* Actual scratch location is at 128 bytes offset */ + scratch_addr = intel_get_pipe_control_scratch_addr(ring) + 128; + + /* + * WaSendDummy3dPrimitveAfterSetContext:ivb,vlv + * Software must send a pipe_control with a CS stall + * and a post sync operation and then a dummy DRAW after + * every MI_SET_CONTEXT and after any PIPELINE_SELECT that + * is enabling 3D mode. A dummy draw is a 3DPRIMITIVE command + * with Indirect Parameter Enable set to 0, UAV Coherency + * Required set to 0, Predicate Enable set to 0, + * End Offset Enable set to 0, and Vertex Count Per Instance + * set to 0, All other parameters are a don't care. + */ + + /* + * Add a pipe control with CS Stall and postsync op + * before dummy 3D_PRIMITIVE + */ + flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL; + intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4)); + intel_ring_emit(ring, flags); + intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); + intel_ring_emit(ring, 0); + + /* Add a dummy 3D_PRIMITVE */ + intel_ring_emit(ring, GFX_OP_3DPRIMITIVE); + intel_ring_emit(ring, 4); /* PrimTopoType*/ + intel_ring_emit(ring, 0); /* VertexCountPerInstance */ + intel_ring_emit(ring, 0); /* StartVertexLocation */ + intel_ring_emit(ring, 0); /* InstanceCount */ + intel_ring_emit(ring, 0); /* StartInstanceLocation */ + intel_ring_emit(ring, 0); /* BaseVertexLocation */ +} + static inline int mi_set_context(struct intel_ring_buffer *ring, struct i915_hw_context *new_context, @@ -563,7 +604,10 @@ mi_set_context(struct intel_ring_buffer *ring, return ret; } - ret = intel_ring_begin(ring, 6); + if (INTEL_INFO(ring->dev)->gen == 7) + ret = intel_ring_begin(ring, 6+4+8); + else + ret = intel_ring_begin(ring, 6); if (ret) return ret; @@ -586,8 +630,15 @@ mi_set_context(struct intel_ring_buffer *ring, */ intel_ring_emit(ring, MI_NOOP); + /* WaSendDummy3dPrimitveAfterSetContext:ivb,vlv */ if (INTEL_INFO(ring->dev)->gen >= 7) - intel_ring_emit(ring, MI_ARB_ON_OFF | MI_ARB_ENABLE); + if (INTEL_INFO(ring->dev)->gen == 7) { + mi_set_context_dummy3d_prim_wa(ring); + intel_ring_emit(ring, MI_ARB_ON_OFF | MI_ARB_ENABLE); + intel_ring_emit(ring, MI_NOOP); + } else + intel_ring_emit(ring, MI_ARB_ON_OFF | MI_ARB_ENABLE); + else intel_ring_emit(ring, MI_NOOP); diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 8f84555..1128527 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -355,6 +355,7 @@ #define PIPE_CONTROL_STALL_AT_SCOREBOARD (1<<1) #define PIPE_CONTROL_DEPTH_CACHE_FLUSH (1<<0) #define PIPE_CONTROL_GLOBAL_GTT (1<<2) /* in addr dword */ +#define GFX_OP_3DPRIMITIVE ((0x3<<29)|(0x3<<27)|(0x3<<24)|(7-2)) /* * Commands used only by the command parser diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index eb3dd26..834411b 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -585,6 +585,15 @@ err: return ret; } +u32 +intel_get_pipe_control_scratch_addr(struct intel_ring_buffer *ring) +{ + if (ring->scratch.obj == NULL) + return 0; + + return ring->scratch.gtt_offset; +} + static int init_render_ring(struct intel_ring_buffer *ring) { struct drm_device *dev = ring->dev; diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h index 413cdc7..ffaed8b 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.h +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h @@ -291,6 +291,7 @@ int intel_init_vebox_ring_buffer(struct drm_device *dev); u64 intel_ring_get_active_head(struct intel_ring_buffer *ring); void intel_ring_setup_status_page(struct intel_ring_buffer *ring); +u32 intel_get_pipe_control_scratch_addr(struct intel_ring_buffer *ring); static inline u32 intel_ring_get_tail(struct intel_ring_buffer *ring) {