From patchwork Tue Apr 15 02:38:47 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Zhao, Yakui" X-Patchwork-Id: 3988181 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 57A34C0DA2 for ; Tue, 15 Apr 2014 01:31:42 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 4DF9A20200 for ; Tue, 15 Apr 2014 01:31:41 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 4763920120 for ; Tue, 15 Apr 2014 01:31:39 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 95D016E136; Mon, 14 Apr 2014 18:31:37 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga03.intel.com (mga03.intel.com [143.182.124.21]) by gabe.freedesktop.org (Postfix) with ESMTP id 734C889DD5 for ; Mon, 14 Apr 2014 18:31:36 -0700 (PDT) Received: from azsmga001.ch.intel.com ([10.2.17.19]) by azsmga101.ch.intel.com with ESMTP; 14 Apr 2014 18:31:35 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="4.97,861,1389772800"; d="scan'208";a="419000833" Received: from hb-ws.sh.intel.com (HELO localhost.localdomain.sh.intel.com) ([10.239.13.109]) by azsmga001.ch.intel.com with ESMTP; 14 Apr 2014 18:31:21 -0700 From: Zhao Yakui To: intel-gfx@lists.freedesktop.org Date: Tue, 15 Apr 2014 10:38:47 +0800 Message-Id: <1397529528-7114-2-git-send-email-yakui.zhao@intel.com> X-Mailer: git-send-email 1.7.10.1 In-Reply-To: <1397529528-7114-1-git-send-email-yakui.zhao@intel.com> References: <1397529528-7114-1-git-send-email-yakui.zhao@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] =?utf-8?q?=5BPATCH_I-g-t_V2_1/2=5D_tests=3A_Add_one_r?= =?utf-8?q?ing_sync_case_based_on_multi_drm=5Ffd_to_test_ring_semap?= =?utf-8?q?hore_sync_under_multi_BSD_rings?= X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-5.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The Broadwell GT3 machine has two independent BSD rings in kernel driver while it is transparent to the user-space driver. In such case it needs to check the ring sync between the two BSD rings. At the same time it also needs to check the sync among the second BSD ring and the other rings. Signed-off-by: Zhao Yakui Reviewed-by: Imre Deak --- tests/Makefile.sources | 1 + tests/gem_multi_bsd_sync_loop.c | 172 +++++++++++++++++++++++++++++++++++++++ 2 files changed, 173 insertions(+) create mode 100644 tests/gem_multi_bsd_sync_loop.c diff --git a/tests/Makefile.sources b/tests/Makefile.sources index c957ace..7cd9ca8 100644 --- a/tests/Makefile.sources +++ b/tests/Makefile.sources @@ -105,6 +105,7 @@ TESTS_progs = \ gem_render_tiled_blits \ gem_ring_sync_copy \ gem_ring_sync_loop \ + gem_multi_bsd_sync_loop \ gem_seqno_wrap \ gem_set_tiling_vs_gtt \ gem_set_tiling_vs_pwrite \ diff --git a/tests/gem_multi_bsd_sync_loop.c b/tests/gem_multi_bsd_sync_loop.c new file mode 100644 index 0000000..7f5b832 --- /dev/null +++ b/tests/gem_multi_bsd_sync_loop.c @@ -0,0 +1,172 @@ +/* + * Copyright © 2014 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + * Authors: + * Daniel Vetter (based on gem_ring_sync_loop_*.c) + * Zhao Yakui + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include "drm.h" +#include "ioctl_wrappers.h" +#include "drmtest.h" +#include "intel_bufmgr.h" +#include "intel_batchbuffer.h" +#include "intel_io.h" +#include "i830_reg.h" +#include "intel_chipset.h" + +static drm_intel_bufmgr *bufmgr; +struct intel_batchbuffer *batch; +static drm_intel_bo *target_buffer; + +#define NUM_FD 50 + +static int mfd[NUM_FD]; +static drm_intel_bufmgr *mbufmgr[NUM_FD]; +static struct intel_batchbuffer *mbatch[NUM_FD]; +static drm_intel_bo *mbuffer[NUM_FD]; + + +/* + * Testcase: Basic check of ring<->ring sync using a dummy reloc + * + * Extremely efficient at catching missed irqs with semaphores=0 ... + */ + +#define MI_COND_BATCH_BUFFER_END (0x36<<23 | 1) +#define MI_DO_COMPARE (1<<21) + +static void +store_dword_loop(int fd) +{ + int i; + int num_rings = gem_get_num_rings(fd); + + srandom(0xdeadbeef); + + for (i = 0; i < SLOW_QUICK(0x100000, 10); i++) { + int ring, mindex; + ring = random() % num_rings + 1; + mindex = random() % NUM_FD; + batch = mbatch[mindex]; + if (ring == I915_EXEC_RENDER) { + BEGIN_BATCH(4); + OUT_BATCH(MI_COND_BATCH_BUFFER_END | MI_DO_COMPARE); + OUT_BATCH(0xffffffff); /* compare dword */ + OUT_RELOC(mbuffer[mindex], I915_GEM_DOMAIN_RENDER, + I915_GEM_DOMAIN_RENDER, 0); + OUT_BATCH(MI_NOOP); + ADVANCE_BATCH(); + } else { + BEGIN_BATCH(4); + OUT_BATCH(MI_FLUSH_DW | 1); + OUT_BATCH(0); /* reserved */ + OUT_RELOC(mbuffer[mindex], I915_GEM_DOMAIN_RENDER, + I915_GEM_DOMAIN_RENDER, 0); + OUT_BATCH(MI_NOOP | (1<<22) | (0xf)); + ADVANCE_BATCH(); + } + intel_batchbuffer_flush_on_ring(batch, ring); + } + + drm_intel_bo_map(target_buffer, 0); + // map to force waiting on rendering + drm_intel_bo_unmap(target_buffer); +} + +igt_simple_main +{ + int fd; + int devid; + int i; + + fd = drm_open_any(); + devid = intel_get_drm_devid(fd); + gem_require_ring(fd, I915_EXEC_BLT); + + + bufmgr = drm_intel_bufmgr_gem_init(fd, 4096); + igt_assert(bufmgr); + drm_intel_bufmgr_gem_enable_reuse(bufmgr); + + + target_buffer = drm_intel_bo_alloc(bufmgr, "target bo", 4096, 4096); + igt_assert(target_buffer); + + /* Create multiple drm_fd and map one gem_object among multi drm_fd */ + { + unsigned int target_flink; + char buffer_name[32]; + if (dri_bo_flink(target_buffer, &target_flink)) { + igt_assert(0); + printf("fail to get flink for target buffer\n"); + goto fail_flink; + } + for (i = 0; i < NUM_FD; i++) { + mfd[i] = 0; + mbufmgr[i] = NULL; + mbuffer[i] = NULL; + } + for (i = 0; i < NUM_FD; i++) { + sprintf(buffer_name, "Target buffer %d\n", i); + mfd[i] = drm_open_any(); + mbufmgr[i] = drm_intel_bufmgr_gem_init(mfd[i], 4096); + igt_assert(mbufmgr[i]); + drm_intel_bufmgr_gem_enable_reuse(mbufmgr[i]); + mbatch[i] = intel_batchbuffer_alloc(mbufmgr[i], devid); + igt_assert(mbufmgr[i]); + mbuffer[i] = intel_bo_gem_create_from_name(mbufmgr[i], buffer_name, target_flink); + igt_assert(mbuffer[i]); + } + } + + store_dword_loop(fd); + + { + for (i = 0; i < NUM_FD; i++) { + dri_bo_unreference(mbuffer[i]); + intel_batchbuffer_free(mbatch[i]); + drm_intel_bufmgr_destroy(mbufmgr[i]); + close(mfd[i]); + } + } + drm_intel_bo_unreference(target_buffer); + drm_intel_bufmgr_destroy(bufmgr); + + close(fd); + return; + +fail_flink: + drm_intel_bo_unreference(target_buffer); + drm_intel_bufmgr_destroy(bufmgr); + + close(fd); +}