| Message ID | 1397855070-4480-12-git-send-email-rodrigo.vivi@gmail.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Fri, Apr 18, 2014 at 02:04:27PM -0700, Rodrigo Vivi wrote: > From: Ben Widawsky <benjamin.widawsky@intel.com> > > I don't have any insight on what parts can do what. The docs do seem to > suggest WT caching works in at least the same manner as it doesn't on > Haswell. As Ben previously mentioned, s/doesn't/does. Other than that, looks good Reviewed-by: Brad Volkin <bradley.d.volkin@intel.com> > > The addr = 0 is to shut up GCC: > drivers/gpu/drm/i915/i915_gem_gtt.c:80:7: warning: 'addr' may be used > uninitialized in this function [-Wmaybe-uninitialized] > > Signed-off-by: Ben Widawsky <ben@bwidawsk.net> > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@gmail.com> > --- > drivers/gpu/drm/i915/i915_drv.h | 11 ++++++----- > drivers/gpu/drm/i915/i915_gem_gtt.c | 17 +++++++++++++---- > 2 files changed, 19 insertions(+), 9 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h > index 4e81ce1..2bc6745 100644 > --- a/drivers/gpu/drm/i915/i915_drv.h > +++ b/drivers/gpu/drm/i915/i915_drv.h > @@ -1835,11 +1835,12 @@ struct drm_i915_cmd_table { > #define BSD_RING (1<<VCS) > #define BLT_RING (1<<BCS) > #define VEBOX_RING (1<<VECS) > -#define HAS_BSD(dev) (INTEL_INFO(dev)->ring_mask & BSD_RING) > -#define HAS_BLT(dev) (INTEL_INFO(dev)->ring_mask & BLT_RING) > -#define HAS_VEBOX(dev) (INTEL_INFO(dev)->ring_mask & VEBOX_RING) > -#define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc) > -#define HAS_WT(dev) (IS_HASWELL(dev) && to_i915(dev)->ellc_size) > +#define HAS_BSD(dev) (INTEL_INFO(dev)->ring_mask & BSD_RING) > +#define HAS_BLT(dev) (INTEL_INFO(dev)->ring_mask & BLT_RING) > +#define HAS_VEBOX(dev) (INTEL_INFO(dev)->ring_mask & VEBOX_RING) > +#define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc) > +#define HAS_WT(dev) ((IS_HASWELL(dev) || IS_BROADWELL(dev)) && \ > + to_i915(dev)->ellc_size) > #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws) > > #define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6) > diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c > index 0d514ff..4969162 100644 > --- a/drivers/gpu/drm/i915/i915_gem_gtt.c > +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c > @@ -68,10 +68,19 @@ static inline gen8_gtt_pte_t gen8_pte_encode(dma_addr_t addr, > { > gen8_gtt_pte_t pte = valid ? _PAGE_PRESENT | _PAGE_RW : 0; > pte |= addr; > - if (level != I915_CACHE_NONE) > - pte |= PPAT_CACHED_INDEX; > - else > + > + switch (level) { > + case I915_CACHE_NONE: > pte |= PPAT_UNCACHED_INDEX; > + break; > + case I915_CACHE_WT: > + pte |= PPAT_DISPLAY_ELLC_INDEX; > + break; > + default: > + pte |= PPAT_CACHED_INDEX; > + break; > + } > + > return pte; > } > > @@ -1368,7 +1377,7 @@ static void gen8_ggtt_insert_entries(struct i915_address_space *vm, > (gen8_gtt_pte_t __iomem *)dev_priv->gtt.gsm + first_entry; > int i = 0; > struct sg_page_iter sg_iter; > - dma_addr_t addr; > + dma_addr_t addr = 0; > > for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) { > addr = sg_dma_address(sg_iter.sg) + > -- > 1.8.3.1 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 4e81ce1..2bc6745 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1835,11 +1835,12 @@ struct drm_i915_cmd_table { #define BSD_RING (1<<VCS) #define BLT_RING (1<<BCS) #define VEBOX_RING (1<<VECS) -#define HAS_BSD(dev) (INTEL_INFO(dev)->ring_mask & BSD_RING) -#define HAS_BLT(dev) (INTEL_INFO(dev)->ring_mask & BLT_RING) -#define HAS_VEBOX(dev) (INTEL_INFO(dev)->ring_mask & VEBOX_RING) -#define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc) -#define HAS_WT(dev) (IS_HASWELL(dev) && to_i915(dev)->ellc_size) +#define HAS_BSD(dev) (INTEL_INFO(dev)->ring_mask & BSD_RING) +#define HAS_BLT(dev) (INTEL_INFO(dev)->ring_mask & BLT_RING) +#define HAS_VEBOX(dev) (INTEL_INFO(dev)->ring_mask & VEBOX_RING) +#define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc) +#define HAS_WT(dev) ((IS_HASWELL(dev) || IS_BROADWELL(dev)) && \ + to_i915(dev)->ellc_size) #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws) #define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6) diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c index 0d514ff..4969162 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.c +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c @@ -68,10 +68,19 @@ static inline gen8_gtt_pte_t gen8_pte_encode(dma_addr_t addr, { gen8_gtt_pte_t pte = valid ? _PAGE_PRESENT | _PAGE_RW : 0; pte |= addr; - if (level != I915_CACHE_NONE) - pte |= PPAT_CACHED_INDEX; - else + + switch (level) { + case I915_CACHE_NONE: pte |= PPAT_UNCACHED_INDEX; + break; + case I915_CACHE_WT: + pte |= PPAT_DISPLAY_ELLC_INDEX; + break; + default: + pte |= PPAT_CACHED_INDEX; + break; + } + return pte; } @@ -1368,7 +1377,7 @@ static void gen8_ggtt_insert_entries(struct i915_address_space *vm, (gen8_gtt_pte_t __iomem *)dev_priv->gtt.gsm + first_entry; int i = 0; struct sg_page_iter sg_iter; - dma_addr_t addr; + dma_addr_t addr = 0; for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) { addr = sg_dma_address(sg_iter.sg) +