diff mbox

[12/14] drm/i915/bdw: enable eDRAM.

Message ID 1397855070-4480-13-git-send-email-rodrigo.vivi@gmail.com (mailing list archive)
State New, archived
Headers show

Commit Message

Rodrigo Vivi April 18, 2014, 9:04 p.m. UTC
From: Ben Widawsky <benjamin.widawsky@intel.com>

The same register exists for querying and programming eDRAM AKA eLLC. So
we can simply use it. For now, use all the same defaults as we had
for Haswell, since like Haswell, I have no further details.

I do not actually have a part with eDRAM, so I cannot test this.

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
---
 drivers/gpu/drm/i915/intel_uncore.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Comments

bradley.d.volkin@intel.com April 28, 2014, 4:27 p.m. UTC | #1
Reviewed-by: Brad Volkin <bradley.d.volkin@intel.com>

On Fri, Apr 18, 2014 at 02:04:28PM -0700, Rodrigo Vivi wrote:
> From: Ben Widawsky <benjamin.widawsky@intel.com>
> 
> The same register exists for querying and programming eDRAM AKA eLLC. So
> we can simply use it. For now, use all the same defaults as we had
> for Haswell, since like Haswell, I have no further details.
> 
> I do not actually have a part with eDRAM, so I cannot test this.
> 
> Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
> ---
>  drivers/gpu/drm/i915/intel_uncore.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
> index c8969e3..0e6b502 100644
> --- a/drivers/gpu/drm/i915/intel_uncore.c
> +++ b/drivers/gpu/drm/i915/intel_uncore.c
> @@ -373,7 +373,7 @@ void intel_uncore_early_sanitize(struct drm_device *dev)
>  	if (HAS_FPGA_DBG_UNCLAIMED(dev))
>  		__raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
>  
> -	if (IS_HASWELL(dev) &&
> +	if ((IS_HASWELL(dev) || IS_BROADWELL(dev)) &&
>  	    (__raw_i915_read32(dev_priv, HSW_EDRAM_PRESENT) == 1)) {
>  		/* The docs do not explain exactly how the calculation can be
>  		 * made. It is somewhat guessable, but for now, it's always
> -- 
> 1.8.3.1
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
diff mbox

Patch

diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index c8969e3..0e6b502 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -373,7 +373,7 @@  void intel_uncore_early_sanitize(struct drm_device *dev)
 	if (HAS_FPGA_DBG_UNCLAIMED(dev))
 		__raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
 
-	if (IS_HASWELL(dev) &&
+	if ((IS_HASWELL(dev) || IS_BROADWELL(dev)) &&
 	    (__raw_i915_read32(dev_priv, HSW_EDRAM_PRESENT) == 1)) {
 		/* The docs do not explain exactly how the calculation can be
 		 * made. It is somewhat guessable, but for now, it's always