| Message ID | 1398067454-7581-6-git-send-email-deepak.s@linux.intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
s/Cheeryview/Cherryview On Mon, Apr 21, 2014 at 01:34:09PM +0530, deepak.s@linux.intel.com wrote: > From: Deepak S <deepak.s@linux.intel.com> > > v2: Disable media turbo and Add DOWN_IDLE_AVG support (Ville) > > v3: Mass rename of the dev_priv->rps variables in upstream. > > Signed-off-by: Deepak S <deepak.s@linux.intel.com> > Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> > --- > drivers/gpu/drm/i915/i915_drv.h | 1 + > drivers/gpu/drm/i915/i915_reg.h | 10 +++++ > drivers/gpu/drm/i915/intel_pm.c | 82 ++++++++++++++++++++++++++++++++++- > drivers/gpu/drm/i915/intel_sideband.c | 15 +++++++ > 4 files changed, 107 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h > index 7d6acb4..ead2714 100644 > --- a/drivers/gpu/drm/i915/i915_drv.h > +++ b/drivers/gpu/drm/i915/i915_drv.h > @@ -2542,6 +2542,7 @@ int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val) > u32 vlv_punit_read(struct drm_i915_private *dev_priv, u8 addr); > void vlv_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 val); > u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr); > +u32 chv_nc_read(struct drm_i915_private *dev_priv, u8 addr); > u32 vlv_gpio_nc_read(struct drm_i915_private *dev_priv, u32 reg); > void vlv_gpio_nc_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); > u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg); > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 7090b42..f3042bb 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -475,6 +475,7 @@ > #define VLV_IOSF_DATA (VLV_DISPLAY_BASE + 0x2104) > #define VLV_IOSF_ADDR (VLV_DISPLAY_BASE + 0x2108) > > +#define CHV_IOSF_PORT_NC 0x04 > /* See configdb bunit SB addr map */ > #define BUNIT_REG_BISOC 0x11 > > @@ -520,6 +521,14 @@ enum punit_power_well { > #define PUNIT_FUSE_BUS2 0xf6 /* bits 47:40 */ > #define PUNIT_FUSE_BUS1 0xf5 /* bits 55:48 */ > > +#define CHV_IOSF_NC_FB_GFX_FREQ_FUSE 0xdb > +#define CHV_FB_GFX_MAX_FREQ_FUSE_SHIFT 16 > +#define CHV_FB_GFX_MAX_FREQ_FUSE_MASK 0xff I'm having trouble finding this one. > + > +#define CHV_IOSF_NC_FB_GFX_RPE_FUSE 0xdf > +#define CHV_FB_RPE_FREQ_SHIFT 8 > +#define CHV_FB_RPE_FREQ_MASK 0xff > + Oddly, I found this one, but some places seem to contradict it's meaning. Perhaps I am reading it incorrectly. > #define IOSF_NC_FB_GFX_FREQ_FUSE 0x1c > #define FB_GFX_MAX_FREQ_FUSE_SHIFT 3 > #define FB_GFX_MAX_FREQ_FUSE_MASK 0x000007f8 > @@ -747,6 +756,7 @@ enum punit_power_well { > #define SANDYBRIDGE_FENCE_PITCH_SHIFT 32 > #define GEN7_FENCE_MAX_PITCH_VAL 0x0800 > > + spurious > /* control register for cpu gtt access */ > #define TILECTL 0x101000 > #define TILECTL_SWZCTL (1 << 0) > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > index 421a4cc..b37d108 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -3615,6 +3615,38 @@ void gen6_update_ring_freq(struct drm_device *dev) > } > } > > +int cherryview_rps_max_freq(struct drm_i915_private *dev_priv) > +{ > + u32 val, rp0; > + > + val = chv_nc_read(dev_priv, CHV_IOSF_NC_FB_GFX_FREQ_FUSE); > + > + rp0 = (val >> CHV_FB_GFX_MAX_FREQ_FUSE_SHIFT) & > + CHV_FB_GFX_MAX_FREQ_FUSE_MASK; Looks a bit weird style > + > + return rp0; > +} > + > +static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv) > +{ > + u32 val, rpe; > + > + val = chv_nc_read(dev_priv, CHV_IOSF_NC_FB_GFX_RPE_FUSE); > + rpe = (val >> CHV_FB_RPE_FREQ_SHIFT) & CHV_FB_RPE_FREQ_MASK; > + > + return rpe; > +} > + > +int cherryview_rps_min_freq(struct drm_i915_private *dev_priv) > +{ > + u32 val, rpn; > + > + val = chv_nc_read(dev_priv, CHV_IOSF_NC_FB_GFX_FREQ_FUSE); > + rpn = (val >> CHV_FB_RPE_FREQ_SHIFT) & CHV_FB_RPE_FREQ_MASK; > + > + return rpn; > +} > + Is this actually min? I think it's looks a lot better to just call cherryview_rps_rpe_freq() from this function instead of copy pasting the code. > int valleyview_rps_max_freq(struct drm_i915_private *dev_priv) > { > u32 val, rp0; > @@ -3735,7 +3767,7 @@ static void cherryview_enable_rps(struct drm_device *dev) > { > struct drm_i915_private *dev_priv = dev->dev_private; > struct intel_ring_buffer *ring; > - u32 gtfifodbg, rc6_mode = 0, pcbr; > + u32 gtfifodbg, val, rc6_mode = 0, pcbr; > int i; > > WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); > @@ -3783,6 +3815,54 @@ static void cherryview_enable_rps(struct drm_device *dev) > > I915_WRITE(GEN6_RC_CONTROL, rc6_mode); > > + /* 4 Program defaults and thresholds for RPS*/ > + I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400); > + I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000); > + I915_WRITE(GEN6_RP_UP_EI, 66000); > + I915_WRITE(GEN6_RP_DOWN_EI, 350000); > + > + I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10); > + > + /* 5: Enable RPS */ > + I915_WRITE(GEN6_RP_CONTROL, > + GEN6_RP_MEDIA_HW_NORMAL_MODE | > + GEN6_RP_MEDIA_IS_GFX | > + GEN6_RP_ENABLE | > + GEN6_RP_UP_BUSY_AVG | > + GEN6_RP_DOWN_IDLE_AVG); > + > + val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); > + > + DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & 0x10 ? "yes" : "no"); > + DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val); > + > + dev_priv->rps.cur_freq = (val >> 8) & 0xff; > + DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n", > + vlv_gpu_freq(dev_priv, dev_priv->rps.cur_freq), > + dev_priv->rps.cur_freq); > + > + dev_priv->rps.max_freq_softlimit = cherryview_rps_max_freq(dev_priv); > + dev_priv->rps.max_freq = dev_priv->rps.max_freq_softlimit; > + DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n", > + vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit), > + dev_priv->rps.max_freq_softlimit); > + > + dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv); > + DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n", > + vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq), > + dev_priv->rps.efficient_freq); > + > + dev_priv->rps.min_freq_softlimit = cherryview_rps_min_freq(dev_priv); > + DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n", > + vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit), > + dev_priv->rps.min_freq_softlimit); > + > + DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n", > + vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq), > + dev_priv->rps.efficient_freq); > + > + valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq); > + > gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL); > } > > diff --git a/drivers/gpu/drm/i915/intel_sideband.c b/drivers/gpu/drm/i915/intel_sideband.c > index b1a5514..8f6904d 100644 > --- a/drivers/gpu/drm/i915/intel_sideband.c > +++ b/drivers/gpu/drm/i915/intel_sideband.c > @@ -106,6 +106,21 @@ void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val) > PUNIT_OPCODE_REG_WRITE, reg, &val); > } > > +u32 chv_nc_read(struct drm_i915_private *dev_priv, u8 addr) > +{ > + u32 val = 0; > + > + WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); > + > + mutex_lock(&dev_priv->dpio_lock); > + vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), CHV_IOSF_PORT_NC, > + PUNIT_OPCODE_REG_READ, addr, &val); > + mutex_unlock(&dev_priv->dpio_lock); > + > + return val; > +} > + > + > u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr) > { > u32 val = 0; Looks fine as an enabling patch hidden behind prelim HW. I need some more info/help to do a proper review. Acked-by: Ben Widawsky <ben@bwidawsk.net>
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 7d6acb4..ead2714 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -2542,6 +2542,7 @@ int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val) u32 vlv_punit_read(struct drm_i915_private *dev_priv, u8 addr); void vlv_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 val); u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr); +u32 chv_nc_read(struct drm_i915_private *dev_priv, u8 addr); u32 vlv_gpio_nc_read(struct drm_i915_private *dev_priv, u32 reg); void vlv_gpio_nc_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg); diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 7090b42..f3042bb 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -475,6 +475,7 @@ #define VLV_IOSF_DATA (VLV_DISPLAY_BASE + 0x2104) #define VLV_IOSF_ADDR (VLV_DISPLAY_BASE + 0x2108) +#define CHV_IOSF_PORT_NC 0x04 /* See configdb bunit SB addr map */ #define BUNIT_REG_BISOC 0x11 @@ -520,6 +521,14 @@ enum punit_power_well { #define PUNIT_FUSE_BUS2 0xf6 /* bits 47:40 */ #define PUNIT_FUSE_BUS1 0xf5 /* bits 55:48 */ +#define CHV_IOSF_NC_FB_GFX_FREQ_FUSE 0xdb +#define CHV_FB_GFX_MAX_FREQ_FUSE_SHIFT 16 +#define CHV_FB_GFX_MAX_FREQ_FUSE_MASK 0xff + +#define CHV_IOSF_NC_FB_GFX_RPE_FUSE 0xdf +#define CHV_FB_RPE_FREQ_SHIFT 8 +#define CHV_FB_RPE_FREQ_MASK 0xff + #define IOSF_NC_FB_GFX_FREQ_FUSE 0x1c #define FB_GFX_MAX_FREQ_FUSE_SHIFT 3 #define FB_GFX_MAX_FREQ_FUSE_MASK 0x000007f8 @@ -747,6 +756,7 @@ enum punit_power_well { #define SANDYBRIDGE_FENCE_PITCH_SHIFT 32 #define GEN7_FENCE_MAX_PITCH_VAL 0x0800 + /* control register for cpu gtt access */ #define TILECTL 0x101000 #define TILECTL_SWZCTL (1 << 0) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 421a4cc..b37d108 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -3615,6 +3615,38 @@ void gen6_update_ring_freq(struct drm_device *dev) } } +int cherryview_rps_max_freq(struct drm_i915_private *dev_priv) +{ + u32 val, rp0; + + val = chv_nc_read(dev_priv, CHV_IOSF_NC_FB_GFX_FREQ_FUSE); + + rp0 = (val >> CHV_FB_GFX_MAX_FREQ_FUSE_SHIFT) & + CHV_FB_GFX_MAX_FREQ_FUSE_MASK; + + return rp0; +} + +static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv) +{ + u32 val, rpe; + + val = chv_nc_read(dev_priv, CHV_IOSF_NC_FB_GFX_RPE_FUSE); + rpe = (val >> CHV_FB_RPE_FREQ_SHIFT) & CHV_FB_RPE_FREQ_MASK; + + return rpe; +} + +int cherryview_rps_min_freq(struct drm_i915_private *dev_priv) +{ + u32 val, rpn; + + val = chv_nc_read(dev_priv, CHV_IOSF_NC_FB_GFX_FREQ_FUSE); + rpn = (val >> CHV_FB_RPE_FREQ_SHIFT) & CHV_FB_RPE_FREQ_MASK; + + return rpn; +} + int valleyview_rps_max_freq(struct drm_i915_private *dev_priv) { u32 val, rp0; @@ -3735,7 +3767,7 @@ static void cherryview_enable_rps(struct drm_device *dev) { struct drm_i915_private *dev_priv = dev->dev_private; struct intel_ring_buffer *ring; - u32 gtfifodbg, rc6_mode = 0, pcbr; + u32 gtfifodbg, val, rc6_mode = 0, pcbr; int i; WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); @@ -3783,6 +3815,54 @@ static void cherryview_enable_rps(struct drm_device *dev) I915_WRITE(GEN6_RC_CONTROL, rc6_mode); + /* 4 Program defaults and thresholds for RPS*/ + I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400); + I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000); + I915_WRITE(GEN6_RP_UP_EI, 66000); + I915_WRITE(GEN6_RP_DOWN_EI, 350000); + + I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10); + + /* 5: Enable RPS */ + I915_WRITE(GEN6_RP_CONTROL, + GEN6_RP_MEDIA_HW_NORMAL_MODE | + GEN6_RP_MEDIA_IS_GFX | + GEN6_RP_ENABLE | + GEN6_RP_UP_BUSY_AVG | + GEN6_RP_DOWN_IDLE_AVG); + + val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); + + DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & 0x10 ? "yes" : "no"); + DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val); + + dev_priv->rps.cur_freq = (val >> 8) & 0xff; + DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n", + vlv_gpu_freq(dev_priv, dev_priv->rps.cur_freq), + dev_priv->rps.cur_freq); + + dev_priv->rps.max_freq_softlimit = cherryview_rps_max_freq(dev_priv); + dev_priv->rps.max_freq = dev_priv->rps.max_freq_softlimit; + DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n", + vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit), + dev_priv->rps.max_freq_softlimit); + + dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv); + DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n", + vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq), + dev_priv->rps.efficient_freq); + + dev_priv->rps.min_freq_softlimit = cherryview_rps_min_freq(dev_priv); + DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n", + vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit), + dev_priv->rps.min_freq_softlimit); + + DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n", + vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq), + dev_priv->rps.efficient_freq); + + valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq); + gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL); } diff --git a/drivers/gpu/drm/i915/intel_sideband.c b/drivers/gpu/drm/i915/intel_sideband.c index b1a5514..8f6904d 100644 --- a/drivers/gpu/drm/i915/intel_sideband.c +++ b/drivers/gpu/drm/i915/intel_sideband.c @@ -106,6 +106,21 @@ void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val) PUNIT_OPCODE_REG_WRITE, reg, &val); } +u32 chv_nc_read(struct drm_i915_private *dev_priv, u8 addr) +{ + u32 val = 0; + + WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); + + mutex_lock(&dev_priv->dpio_lock); + vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), CHV_IOSF_PORT_NC, + PUNIT_OPCODE_REG_READ, addr, &val); + mutex_unlock(&dev_priv->dpio_lock); + + return val; +} + + u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr) { u32 val = 0;