From patchwork Mon Apr 21 08:04:10 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: deepak.s@linux.intel.com X-Patchwork-Id: 4022931 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 6E0E8BFF02 for ; Mon, 21 Apr 2014 08:04:57 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 899E3202EB for ; Mon, 21 Apr 2014 08:04:56 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 719C4202BE for ; Mon, 21 Apr 2014 08:04:55 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id E7DF66E2E3; Mon, 21 Apr 2014 01:04:53 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTP id 1A22D6E2DB for ; Mon, 21 Apr 2014 01:04:50 -0700 (PDT) Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga102.jf.intel.com with ESMTP; 21 Apr 2014 00:59:59 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="4.97,895,1389772800"; d="scan'208";a="516563960" Received: from ds1-mobl1.gar.corp.intel.com (HELO deepaks.iind.intel.com) ([10.223.184.130]) by fmsmga001.fm.intel.com with ESMTP; 21 Apr 2014 01:04:38 -0700 From: deepak.s@linux.intel.com To: intel-gfx@lists.freedesktop.org Date: Mon, 21 Apr 2014 13:34:10 +0530 Message-Id: <1398067454-7581-7-git-send-email-deepak.s@linux.intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1398067454-7581-2-git-send-email-deepak.s@linux.intel.com> References: <1398067454-7581-2-git-send-email-deepak.s@linux.intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 06/10] drm/i915/chv: Streamline CHV forcewake stuff X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.8 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Ville Syrjälä Streamline the CHV forcewake functions just like was done for VLV. This will also fix a bug in accessing the common well registers, where we'd end up trying to wake up the wells too many times since we'd call force_wake_get/put twice per register access, with FORCEFAKE_ALL both times. Reviewed-by: Mika Kuoppala Signed-off-by: Ville Syrjälä Reviewed-by: Ben Widawsky --- drivers/gpu/drm/i915/intel_uncore.c | 88 ++++++++++++++----------------------- 1 file changed, 32 insertions(+), 56 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c index 11741e4..f1264e2 100644 --- a/drivers/gpu/drm/i915/intel_uncore.c +++ b/drivers/gpu/drm/i915/intel_uncore.c @@ -619,35 +619,22 @@ chv_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \ unsigned fwengine = 0; \ REG_READ_HEADER(x); \ if (FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg)) { \ - fwengine = FORCEWAKE_RENDER; \ - } \ - else if (FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg)) { \ - fwengine = FORCEWAKE_MEDIA; \ - } \ - else if (FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg)) { \ - fwengine = FORCEWAKE_ALL; \ - } \ - if (FORCEWAKE_RENDER & fwengine) { \ - if (dev_priv->uncore.fw_rendercount++ == 0) \ - (dev_priv)->uncore.funcs.force_wake_get(dev_priv, \ - fwengine); \ - } \ - if (FORCEWAKE_MEDIA & fwengine) { \ - if (dev_priv->uncore.fw_mediacount++ == 0) \ - (dev_priv)->uncore.funcs.force_wake_get(dev_priv, \ - fwengine); \ + if (dev_priv->uncore.fw_rendercount == 0) \ + fwengine = FORCEWAKE_RENDER; \ + } else if (FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg)) { \ + if (dev_priv->uncore.fw_mediacount == 0) \ + fwengine = FORCEWAKE_MEDIA; \ + } else if (FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg)) { \ + if (dev_priv->uncore.fw_rendercount == 0) \ + fwengine |= FORCEWAKE_RENDER; \ + if (dev_priv->uncore.fw_mediacount == 0) \ + fwengine |= FORCEWAKE_MEDIA; \ } \ + if (fwengine) \ + dev_priv->uncore.funcs.force_wake_get(dev_priv, fwengine); \ val = __raw_i915_read##x(dev_priv, reg); \ - if (FORCEWAKE_RENDER & fwengine) { \ - if (--dev_priv->uncore.fw_rendercount == 0) \ - (dev_priv)->uncore.funcs.force_wake_put(dev_priv, \ - fwengine); \ - } \ - if (FORCEWAKE_MEDIA & fwengine) { \ - if (--dev_priv->uncore.fw_mediacount == 0) \ - (dev_priv)->uncore.funcs.force_wake_put(dev_priv, \ - fwengine); \ - } \ + if (fwengine) \ + dev_priv->uncore.funcs.force_wake_put(dev_priv, fwengine); \ REG_READ_FOOTER; \ } @@ -781,38 +768,27 @@ gen8_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace static void \ chv_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \ unsigned fwengine = 0; \ - bool __needs_put = !is_gen8_shadowed(dev_priv, reg); \ + bool shadowed = is_gen8_shadowed(dev_priv, reg); \ REG_WRITE_HEADER; \ - if (FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg)) { \ - fwengine = FORCEWAKE_RENDER; \ - } \ - else if (FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg)) { \ - fwengine = FORCEWAKE_MEDIA; \ - } \ - else if (FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg)) { \ - fwengine = FORCEWAKE_ALL; \ - } \ - if (__needs_put && (FORCEWAKE_RENDER & fwengine)) { \ - if (dev_priv->uncore.fw_rendercount++ == 0) \ - (dev_priv)->uncore.funcs.force_wake_get(dev_priv, \ - fwengine); \ - } \ - if (__needs_put && (FORCEWAKE_MEDIA & fwengine)) { \ - if (dev_priv->uncore.fw_mediacount++ == 0) \ - (dev_priv)->uncore.funcs.force_wake_get(dev_priv, \ - fwengine); \ + if (!shadowed) { \ + if (FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg)) { \ + if (dev_priv->uncore.fw_rendercount == 0) \ + fwengine = FORCEWAKE_RENDER; \ + } else if (FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg)) { \ + if (dev_priv->uncore.fw_mediacount == 0) \ + fwengine = FORCEWAKE_MEDIA; \ + } else if (FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg)) { \ + if (dev_priv->uncore.fw_rendercount == 0) \ + fwengine |= FORCEWAKE_RENDER; \ + if (dev_priv->uncore.fw_mediacount == 0) \ + fwengine |= FORCEWAKE_MEDIA; \ + } \ } \ + if (fwengine) \ + dev_priv->uncore.funcs.force_wake_get(dev_priv, fwengine); \ __raw_i915_write##x(dev_priv, reg, val); \ - if (__needs_put && (FORCEWAKE_RENDER & fwengine)) { \ - if (--dev_priv->uncore.fw_rendercount == 0) \ - (dev_priv)->uncore.funcs.force_wake_put(dev_priv, \ - fwengine); \ - } \ - if (__needs_put && (FORCEWAKE_MEDIA & fwengine)) { \ - if (--dev_priv->uncore.fw_mediacount == 0) \ - (dev_priv)->uncore.funcs.force_wake_put(dev_priv, \ - fwengine); \ - } \ + if (fwengine) \ + dev_priv->uncore.funcs.force_wake_put(dev_priv, fwengine); \ REG_WRITE_FOOTER; \ }