From patchwork Thu Apr 24 21:22:57 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paulo Zanoni X-Patchwork-Id: 4054041 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 4D79EBFF02 for ; Thu, 24 Apr 2014 21:23:16 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 7B23120351 for ; Thu, 24 Apr 2014 21:23:15 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 9C94B201B9 for ; Thu, 24 Apr 2014 21:23:14 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 76CBB6E0DD; Thu, 24 Apr 2014 14:23:13 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-yh0-f43.google.com (mail-yh0-f43.google.com [209.85.213.43]) by gabe.freedesktop.org (Postfix) with ESMTP id 75BE06E0DD for ; Thu, 24 Apr 2014 14:23:11 -0700 (PDT) Received: by mail-yh0-f43.google.com with SMTP id a41so1574348yho.2 for ; Thu, 24 Apr 2014 14:23:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id; bh=iDVvgn3EVVSPLH/RQ/ivIMqS6XeJ7Ueeejr3Ao+RDSs=; b=gSbxQWLRMcPrYFnBAT5R0MjIG+Qvm8mDg8xfV7WW8K3dJA63oUsiRb4K7M03afz+qw ZRX5K+RD9nOqPPmhLK/F/xjuF4oI7Bb1ltxnvcVTmDfP+8HKDbxDKsWhZ7Xz/uGNn0p6 fHV7gxJxZOeZdHHtTgeLTLWCG781Zv5aMO9327arudz4CquNKWIv5rdTBVP9F8uB+pPz MC6DnoZamY4//tsGScxbUXO7taCQnkaDpaCaSZ+2qHfqm1gqGEOtZjkEBJ1xzekxBIQr NOVFnXEJQ+MECc5n5cky676jBNHFybXGHdCma7j6pcC79Ol+tj+XPl3p3kFhHhnFE8tv W7cw== X-Received: by 10.236.132.134 with SMTP id o6mr5705790yhi.147.1398374590825; Thu, 24 Apr 2014 14:23:10 -0700 (PDT) Received: from localhost.localdomain ([177.16.38.220]) by mx.google.com with ESMTPSA id c27sm9740860yhm.35.2014.04.24.14.23.09 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 24 Apr 2014 14:23:10 -0700 (PDT) From: Paulo Zanoni To: intel-gfx@lists.freedesktop.org Date: Thu, 24 Apr 2014 18:22:57 -0300 Message-Id: <1398374579-5697-1-git-send-email-przanoni@gmail.com> X-Mailer: git-send-email 1.9.0 Cc: Paulo Zanoni Subject: [Intel-gfx] [PATCH 1/3] drm/i915: consider the source max DP lane count too X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.7 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, T_DKIM_INVALID, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Paulo Zanoni Even if the panel claims it can support 4 lanes, there's the possibility that the HW can't, so consider this while selecting the max lane count. Signed-off-by: Paulo Zanoni --- drivers/gpu/drm/i915/intel_dp.c | 20 ++++++++++++++++++-- 1 file changed, 18 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 104998e..19537a6 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -120,6 +120,22 @@ intel_dp_max_link_bw(struct intel_dp *intel_dp) return max_link_bw; } +static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp) +{ + struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); + struct drm_device *dev = intel_dig_port->base.base.dev; + u8 source_max, sink_max; + + source_max = 4; + if (HAS_DDI(dev) && intel_dig_port->port == PORT_A && + (intel_dig_port->saved_port_bits & DDI_A_4_LANES) == 0) + source_max = 2; + + sink_max = drm_dp_max_lane_count(intel_dp->dpcd); + + return min(source_max, sink_max); +} + /* * The units on the numbers in the next two are... bizarre. Examples will * make it clearer; this one parallels an example in the eDP spec. @@ -170,7 +186,7 @@ intel_dp_mode_valid(struct drm_connector *connector, } max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp)); - max_lanes = drm_dp_max_lane_count(intel_dp->dpcd); + max_lanes = intel_dp_max_lane_count(intel_dp); max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes); mode_rate = intel_dp_link_required(target_clock, 18); @@ -764,7 +780,7 @@ intel_dp_compute_config(struct intel_encoder *encoder, struct intel_crtc *intel_crtc = encoder->new_crtc; struct intel_connector *intel_connector = intel_dp->attached_connector; int lane_count, clock; - int max_lane_count = drm_dp_max_lane_count(intel_dp->dpcd); + int max_lane_count = intel_dp_max_lane_count(intel_dp); /* Conveniently, the link BW constants become indices with a shift...*/ int max_clock = intel_dp_max_link_bw(intel_dp) >> 3; int bpp, mode_rate;