From patchwork Thu Apr 24 21:22:59 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paulo Zanoni X-Patchwork-Id: 4054061 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id CE6949F319 for ; Thu, 24 Apr 2014 21:23:24 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id DDB8020351 for ; Thu, 24 Apr 2014 21:23:23 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id CE2B9201B9 for ; Thu, 24 Apr 2014 21:23:22 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 793B96E0FC; Thu, 24 Apr 2014 14:23:22 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-yk0-f172.google.com (mail-yk0-f172.google.com [209.85.160.172]) by gabe.freedesktop.org (Postfix) with ESMTP id 03CA788F9F for ; Thu, 24 Apr 2014 14:23:20 -0700 (PDT) Received: by mail-yk0-f172.google.com with SMTP id q9so1841377ykb.17 for ; Thu, 24 Apr 2014 14:23:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=vNMqK9U2BNNH3Pam8Vy1KwX4C4C/RZIs6nvXl1QUHcw=; b=Jm9gTp7IKXHlbFHiLwF6PDqvtRP/m7R0wjb4iYoUFfquZRg7W2IxO437rYu8JLlCpw T4wGPczf6mLT7PnHAWn1RYxr3lyjbKejJS/rmkaIEBHSYgi2JxX3fCyelwcnAq28qH7L 8U0BEBXA3wGgePJ+Z+eQ54QzBlXuPYDWoB90/8IwtTYPrvHNH5rogxzN02MWa9T58PNa XS7GiJqdTvQ28N4ywNLCdgk26speUMcNT9u+npyVihtyx/+J6Bw5ZY2x+fQps/g8lSoW 24LuZ44H/3o2A/BQSkrCYeUVYn2qX5HC3MjAKhbC4llDkAuODe2oUT7rh5eH6+NkMnj2 5bBw== X-Received: by 10.236.138.136 with SMTP id a8mr5974702yhj.113.1398374600480; Thu, 24 Apr 2014 14:23:20 -0700 (PDT) Received: from localhost.localdomain ([177.16.38.220]) by mx.google.com with ESMTPSA id c27sm9740860yhm.35.2014.04.24.14.23.18 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 24 Apr 2014 14:23:20 -0700 (PDT) From: Paulo Zanoni To: intel-gfx@lists.freedesktop.org Date: Thu, 24 Apr 2014 18:22:59 -0300 Message-Id: <1398374579-5697-3-git-send-email-przanoni@gmail.com> X-Mailer: git-send-email 1.9.0 In-Reply-To: <1398374579-5697-1-git-send-email-przanoni@gmail.com> References: <1398374579-5697-1-git-send-email-przanoni@gmail.com> Cc: Paulo Zanoni Subject: [Intel-gfx] [PATCH 3/3] drm/i915: add i915.dp_link_train_policy option X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.7 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, T_DKIM_INVALID, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Paulo Zanoni We still have way too many bugs with DP link training. We keep switching between "narrow and fast" and "wide and slow", we recently added 5GHz support, and whenever there's a bug report, we have to ask people to apply patches and test them. Wouldn't it be so much better if we could just ask them to boot with some specific Kernel boot option instead of applying a patch? This will move the situation from "i915.ko is completely broken!" to "i915.ko's default values are broken, but there's an option I can set to fix it, so I won't need to learn how to compile a Kernel!". Some useful values: - i915.dp_link_train_policy=1 for "wide and slow" - i915.dp_link_train_policy=0x120 for DP_LINK_BW_2_7 and 2 lanes, which should be able to fit 1920x1080@60Hz and 24bpp - i915.dp_link_train_policy=0x210 to force DP 5GHz testing on not-so-huge modes The default behavior is still the same. Signed-off-by: Paulo Zanoni Reviewed-by: Rafael Barbalho Reviewed-by: Rafael Barbalho --- drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/drm/i915/i915_params.c | 8 ++++++++ drivers/gpu/drm/i915/intel_dp.c | 39 ++++++++++++++++++++++++++++++++++---- 3 files changed, 44 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 7d6acb4..d5ae8dc 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1941,6 +1941,7 @@ struct i915_params { bool reset; bool disable_display; bool disable_vtd_wa; + int dp_link_train_policy; }; extern struct i915_params i915 __read_mostly; diff --git a/drivers/gpu/drm/i915/i915_params.c b/drivers/gpu/drm/i915/i915_params.c index d05a2af..8c358e7 100644 --- a/drivers/gpu/drm/i915/i915_params.c +++ b/drivers/gpu/drm/i915/i915_params.c @@ -48,6 +48,7 @@ struct i915_params i915 __read_mostly = { .disable_display = 0, .enable_cmd_parser = 1, .disable_vtd_wa = 0, + .dp_link_train_policy = 0, }; module_param_named(modeset, i915.modeset, int, 0400); @@ -156,3 +157,10 @@ MODULE_PARM_DESC(disable_vtd_wa, "Disable all VT-d workarounds (default: false)" module_param_named(enable_cmd_parser, i915.enable_cmd_parser, int, 0600); MODULE_PARM_DESC(enable_cmd_parser, "Enable command parsing (1=enabled [default], 0=disabled)"); + +module_param_named(dp_link_train_policy, i915.dp_link_train_policy, int, 0600); +MODULE_PARM_DESC(dp_link_train_policy, + "Choose strategy for DP link training " + "(0=narrow and fast [default], 1=wide and slow. For other values, " + "bits 11:8 are for the BW and bits 7:4 are for the nubmer of lanes, " + "check intel_dp_compute_link_config() for more details.)"); diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 884166b..25f7e1c 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -800,11 +800,42 @@ static bool intel_dp_compute_link_config(int mode_clock, int bpp, mode_rate = intel_dp_link_required(mode_clock, bpp); - for (lanes = min_lanes; lanes <= max_lanes; lanes <<= 1) + switch (i915.dp_link_train_policy) { + case 0: /* Narrow and fast. */ + for (lanes = min_lanes; lanes <= max_lanes; lanes <<= 1) + for (bw_it = min_bw_index; bw_it <= max_bw_index; + bw_it++) + if (link_config_is_possible(mode_rate, lanes, + bws[bw_it])) + goto found; + case 1: /* Wide and slow. */ for (bw_it = min_bw_index; bw_it <= max_bw_index; bw_it++) - if (link_config_is_possible(mode_rate, lanes, - bws[bw_it])) - goto found; + for (lanes = min_lanes; lanes <= max_lanes; lanes <<= 1) + if (link_config_is_possible(mode_rate, lanes, + bws[bw_it])) + goto found; + default: /* Bits 11:8 contain the index of the bws array. + * Bits 7:4 contain the number of lanes. + * Example: i915.dp_link_train_policy=0x140 uses + * DP_LINK_BW_2_7 and 4 lanes. */ + bw_it = (i915.dp_link_train_policy >> 8) & 0xF; + lanes = (i915.dp_link_train_policy >> 4) & 0xF; + + if (bw_it < min_bw_index || bw_it > max_bw_index) { + DRM_ERROR("Invalid BW index\n"); + return false; + } + + if (lanes < min_lanes || lanes > max_lanes || + /* Not a power of two. */ + !(lanes != 0 && (lanes & (lanes - 1)) == 0)) { + DRM_ERROR("Invalid number of lanes.\n"); + return false; + } + + if (link_config_is_possible(mode_rate, lanes, bws[bw_it])) + goto found; + } return false;