| Message ID | 1398738565-6889-1-git-send-email-benjamin.widawsky@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Mon, Apr 28, 2014 at 07:29:25PM -0700, Ben Widawsky wrote: > Previously, our code only had a 32b offset value for where the > batchbuffer starts. With full PPGTT, and 64b canonical GPU address > space, that is an insufficient value. The code to expand is pretty > straight forward, and only one platform needs to do anything with the > extra bits. > > Signed-off-by: Ben Widawsky <ben@bwidawsk.net> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> -Chris
> -----Original Message----- > From: Intel-gfx [mailto:intel-gfx-bounces@lists.freedesktop.org] On Behalf > Of Chris Wilson > Sent: Thursday, May 01, 2014 9:13 AM > To: Widawsky, Benjamin > Cc: Intel GFX > Subject: Re: [Intel-gfx] [PATCH] drm/i915: Support 64b execbuf > > On Mon, Apr 28, 2014 at 07:29:25PM -0700, Ben Widawsky wrote: > > Previously, our code only had a 32b offset value for where the > > batchbuffer starts. With full PPGTT, and 64b canonical GPU address > > space, that is an insufficient value. The code to expand is pretty > > straight forward, and only one platform needs to do anything with the > > extra bits. > > > > Signed-off-by: Ben Widawsky <ben@bwidawsk.net> > Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> -Chris Reviewed-by: Rafael Barbalho <rafael.barbalho@intel.com> Thanks, Rafael
On Thu, May 01, 2014 at 10:18:52AM +0000, Barbalho, Rafael wrote: > > -----Original Message----- > > From: Intel-gfx [mailto:intel-gfx-bounces@lists.freedesktop.org] On Behalf > > Of Chris Wilson > > Sent: Thursday, May 01, 2014 9:13 AM > > To: Widawsky, Benjamin > > Cc: Intel GFX > > Subject: Re: [Intel-gfx] [PATCH] drm/i915: Support 64b execbuf > > > > On Mon, Apr 28, 2014 at 07:29:25PM -0700, Ben Widawsky wrote: > > > Previously, our code only had a 32b offset value for where the > > > batchbuffer starts. With full PPGTT, and 64b canonical GPU address > > > space, that is an insufficient value. The code to expand is pretty > > > straight forward, and only one platform needs to do anything with the > > > extra bits. > > > > > > Signed-off-by: Ben Widawsky <ben@bwidawsk.net> > > Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> -Chris > Reviewed-by: Rafael Barbalho <rafael.barbalho@intel.com> Queued for -next, thanks for the patch. -Daniel
diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c index 6ffecd2..f5f0b92 100644 --- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c +++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c @@ -1017,7 +1017,7 @@ i915_gem_do_execbuffer(struct drm_device *dev, void *data, struct i915_hw_context *ctx; struct i915_address_space *vm; const u32 ctx_id = i915_execbuffer2_get_context_id(*args); - u32 exec_start = args->batch_start_offset, exec_len; + u64 exec_start = args->batch_start_offset, exec_len; u32 mask, flags; int ret, mode, i; bool need_relocs; diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index a42942f..bbe989f 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -1324,7 +1324,7 @@ gen8_ring_put_irq(struct intel_ring_buffer *ring) static int i965_dispatch_execbuffer(struct intel_ring_buffer *ring, - u32 offset, u32 length, + u64 offset, u32 length, unsigned flags) { int ret; @@ -1347,7 +1347,7 @@ i965_dispatch_execbuffer(struct intel_ring_buffer *ring, #define I830_BATCH_LIMIT (256*1024) static int i830_dispatch_execbuffer(struct intel_ring_buffer *ring, - u32 offset, u32 len, + u64 offset, u32 len, unsigned flags) { int ret; @@ -1398,7 +1398,7 @@ i830_dispatch_execbuffer(struct intel_ring_buffer *ring, static int i915_dispatch_execbuffer(struct intel_ring_buffer *ring, - u32 offset, u32 len, + u64 offset, u32 len, unsigned flags) { int ret; @@ -1943,7 +1943,7 @@ static int gen6_bsd_ring_flush(struct intel_ring_buffer *ring, static int gen8_ring_dispatch_execbuffer(struct intel_ring_buffer *ring, - u32 offset, u32 len, + u64 offset, u32 len, unsigned flags) { struct drm_i915_private *dev_priv = ring->dev->dev_private; @@ -1957,8 +1957,8 @@ gen8_ring_dispatch_execbuffer(struct intel_ring_buffer *ring, /* FIXME(BDW): Address space and security selectors. */ intel_ring_emit(ring, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8)); - intel_ring_emit(ring, offset); - intel_ring_emit(ring, 0); + intel_ring_emit(ring, lower_32_bits(offset)); + intel_ring_emit(ring, upper_32_bits(offset)); intel_ring_emit(ring, MI_NOOP); intel_ring_advance(ring); @@ -1967,7 +1967,7 @@ gen8_ring_dispatch_execbuffer(struct intel_ring_buffer *ring, static int hsw_ring_dispatch_execbuffer(struct intel_ring_buffer *ring, - u32 offset, u32 len, + u64 offset, u32 len, unsigned flags) { int ret; @@ -1988,7 +1988,7 @@ hsw_ring_dispatch_execbuffer(struct intel_ring_buffer *ring, static int gen6_ring_dispatch_execbuffer(struct intel_ring_buffer *ring, - u32 offset, u32 len, + u64 offset, u32 len, unsigned flags) { int ret; diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h index dbdce5f..cb55cff 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.h +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h @@ -135,7 +135,7 @@ struct intel_ring_buffer { void (*set_seqno)(struct intel_ring_buffer *ring, u32 seqno); int (*dispatch_execbuffer)(struct intel_ring_buffer *ring, - u32 offset, u32 length, + u64 offset, u32 length, unsigned flags); #define I915_DISPATCH_SECURE 0x1 #define I915_DISPATCH_PINNED 0x2
Previously, our code only had a 32b offset value for where the batchbuffer starts. With full PPGTT, and 64b canonical GPU address space, that is an insufficient value. The code to expand is pretty straight forward, and only one platform needs to do anything with the extra bits. Signed-off-by: Ben Widawsky <ben@bwidawsk.net> --- drivers/gpu/drm/i915/i915_gem_execbuffer.c | 2 +- drivers/gpu/drm/i915/intel_ringbuffer.c | 16 ++++++++-------- drivers/gpu/drm/i915/intel_ringbuffer.h | 2 +- 3 files changed, 10 insertions(+), 10 deletions(-)