From patchwork Tue Apr 29 23:41:19 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dave Airlie X-Patchwork-Id: 4089681 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id CD8F6BFF02 for ; Tue, 29 Apr 2014 23:41:26 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id D89AB20200 for ; Tue, 29 Apr 2014 23:41:25 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id E01EC201B4 for ; Tue, 29 Apr 2014 23:41:24 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 5891A6EAF7; Tue, 29 Apr 2014 16:41:24 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mx1.redhat.com (mx1.redhat.com [209.132.183.28]) by gabe.freedesktop.org (Postfix) with ESMTP id C5D616EAF7 for ; Tue, 29 Apr 2014 16:41:22 -0700 (PDT) Received: from int-mx11.intmail.prod.int.phx2.redhat.com (int-mx11.intmail.prod.int.phx2.redhat.com [10.5.11.24]) by mx1.redhat.com (8.14.4/8.14.4) with ESMTP id s3TNfLmW031039 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK) for ; Tue, 29 Apr 2014 19:41:22 -0400 Received: from dreadlord-bne-redhat-com.bne.redhat.com (dhcp-40-7.bne.redhat.com [10.64.40.7]) by int-mx11.intmail.prod.int.phx2.redhat.com (8.14.4/8.14.4) with ESMTP id s3TNfJGv005573 for ; Tue, 29 Apr 2014 19:41:20 -0400 From: Dave Airlie To: intel-gfx@lists.freedesktop.org Date: Wed, 30 Apr 2014 09:41:19 +1000 Message-Id: <1398814879-3000-1-git-send-email-airlied@gmail.com> X-Scanned-By: MIMEDefang 2.68 on 10.5.11.24 Subject: [Intel-gfx] [PATCH] intel_reg_dumper: add more details for DisplayPort MST regs X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.8 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, FREEMAIL_FROM,RCVD_IN_DNSWL_MED,RP_MATCHES_RCVD,UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Dave Airlie Signed-off-by: Dave Airlie --- tools/intel_reg_dumper.c | 127 ++++++++++++++++++++++++++++++++++++++++++----- 1 file changed, 115 insertions(+), 12 deletions(-) diff --git a/tools/intel_reg_dumper.c b/tools/intel_reg_dumper.c index 4bc299c..a482b5d 100644 --- a/tools/intel_reg_dumper.c +++ b/tools/intel_reg_dumper.c @@ -1685,7 +1685,7 @@ DEBUGSTRING(hsw_debug_sfuse_strap) DEBUGSTRING(hsw_debug_pipe_ddi_func_ctl) { const char *enable, *port, *mode, *bpc, *vsync, *hsync, *edp_input; - const char *width; + const char *width, *payload; enable = (val & (1<<31)) ? "enabled" : "disabled"; @@ -1771,6 +1771,7 @@ DEBUGSTRING(hsw_debug_pipe_ddi_func_ctl) break; } + payload = (val & (1 << 8)) ? "DP VC enable" : "DP VC disable"; switch ((val >> 1) & 7) { case 0: width = "x1"; @@ -1786,8 +1787,110 @@ DEBUGSTRING(hsw_debug_pipe_ddi_func_ctl) break; } - snprintf(result, len, "%s, %s, %s, %s, %s, %s, %s, %s", enable, - port, mode, bpc, vsync, hsync, edp_input, width); + snprintf(result, len, "%s, %s, %s, %s, %s, %s, %s, %s, %s", enable, + port, mode, bpc, vsync, hsync, edp_input, payload, width); +} + +DEBUGSTRING(hsw_debug_dp_tp_ctl) +{ + const char *enable, *mode, *force_act, *enh, *autotrain; + const char *linktrain; + enable = (val & (1<<31)) ? "enabled" : "disabled"; + mode = (val & (1<<27)) ? "MST" : "SST"; + force_act = (val & (1<<25)) ? ", Force ACT" : ""; + enh = (val & (1<<18)) ? ", ENH Framing" : ""; + autotrain = (val & (1<<15)) ? ", Auto training" : ""; + + switch ((val >> 8) & 7) { + case 0: + linktrain = "TP1"; + break; + case 1: + linktrain = "TP2"; + break; + case 2: + linktrain = "Idle"; + break; + case 3: + linktrain = "Normal"; + break; + case 4: + linktrain = "TP3"; + break; + default: + linktrain = "Rsvd"; + break; + } + + snprintf(result, len, "%s, %s %s%s%s%s", enable, mode, force_act, enh, autotrain, linktrain); +} + +DEBUGSTRING(hsw_debug_dp_tp_status) +{ + const char *idle, *active, *mi, *act, *mode, *nstreams; + const char *pm_vc2, *pm_vc1, *pm_vc0; + idle = (val & (1<<27)) ? "Idle sent, " : ""; + active = (val & (1<<26)) ? "Active sent, " : ""; + mi = (val & (1<<25)) ? "Min Idles sent, " : ""; + act = (val & (1<<24)) ? "ACT sent, " : ""; + mode = (val & (1<<23)) ? "MST" : "SST"; + + switch ((val >> 16) & 3) { + case 0: + default: + nstreams = "0 streams"; + break; + case 1: + nstreams = "1 stream"; + break; + case 2: + nstreams = "2 streams"; + break; + case 3: + nstreams = "3 streams"; + break; + } + + switch ((val >> 8) & 3) { + case 0: + default: + pm_vc2 = "VC2-A"; + break; + case 1: + pm_vc2 = "VC2-B"; + break; + case 2: + pm_vc2 = "VC2-C"; + break; + } + + switch ((val >> 4) & 3) { + case 0: + default: + pm_vc1 = "VC1-A"; + break; + case 1: + pm_vc1 = "VC1-B"; + break; + case 2: + pm_vc1 = "VC1-C"; + break; + } + + switch ((val) & 3) { + case 0: + default: + pm_vc0 = "VC0-A"; + break; + case 1: + pm_vc0 = "VC0-B"; + break; + case 2: + pm_vc0 = "VC0-C"; + break; + } + + snprintf(result, len, "%s%s%s%s%s %s %s %s %s", idle, active, mi, act, mode, nstreams, pm_vc2, pm_vc1, pm_vc0); } DEBUGSTRING(hsw_debug_wm_pipe) @@ -2285,17 +2388,17 @@ static struct reg_debug haswell_debug_regs[] = { DEFINEREG2(PIPE_DDI_FUNC_CTL_EDP, hsw_debug_pipe_ddi_func_ctl), /* DP transport control */ - DEFINEREG(DP_TP_CTL_A), - DEFINEREG(DP_TP_CTL_B), - DEFINEREG(DP_TP_CTL_C), - DEFINEREG(DP_TP_CTL_D), - DEFINEREG(DP_TP_CTL_E), + DEFINEREG2(DP_TP_CTL_A, hsw_debug_dp_tp_ctl), + DEFINEREG2(DP_TP_CTL_B, hsw_debug_dp_tp_ctl), + DEFINEREG2(DP_TP_CTL_C, hsw_debug_dp_tp_ctl), + DEFINEREG2(DP_TP_CTL_D, hsw_debug_dp_tp_ctl), + DEFINEREG2(DP_TP_CTL_E, hsw_debug_dp_tp_ctl), /* DP status */ - DEFINEREG(DP_TP_STATUS_B), - DEFINEREG(DP_TP_STATUS_C), - DEFINEREG(DP_TP_STATUS_D), - DEFINEREG(DP_TP_STATUS_E), + DEFINEREG2(DP_TP_STATUS_B, hsw_debug_dp_tp_status), + DEFINEREG2(DP_TP_STATUS_C, hsw_debug_dp_tp_status), + DEFINEREG2(DP_TP_STATUS_D, hsw_debug_dp_tp_status), + DEFINEREG2(DP_TP_STATUS_E, hsw_debug_dp_tp_status), /* DDI buffer control */ DEFINEREG2(DDI_BUF_CTL_A, hsw_debug_ddi_buf_ctl),