From patchwork Mon May 5 08:19:31 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: vandana.kannan@intel.com X-Patchwork-Id: 4112111 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 8A6C1BFF02 for ; Mon, 5 May 2014 08:06:42 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 791FB20221 for ; Mon, 5 May 2014 08:06:41 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 5612F20225 for ; Mon, 5 May 2014 08:06:40 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 655706E75F; Mon, 5 May 2014 01:06:39 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTP id DDC336E75F for ; Mon, 5 May 2014 01:06:37 -0700 (PDT) Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga101.fm.intel.com with ESMTP; 05 May 2014 01:06:19 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="4.97,986,1389772800"; d="scan'208";a="526077600" Received: from vkannan-desktop.iind.intel.com ([10.223.25.35]) by fmsmga001.fm.intel.com with ESMTP; 05 May 2014 01:06:17 -0700 From: Vandana Kannan To: intel-gfx@lists.freedesktop.org Date: Mon, 5 May 2014 13:49:31 +0530 Message-Id: <1399277971-2561-1-git-send-email-vandana.kannan@intel.com> X-Mailer: git-send-email 1.9.2 In-Reply-To: <20140422191526.GA10722@phenom.ffwll.local> References: <20140422191526.GA10722@phenom.ffwll.local> Cc: Daniel Vetter Subject: [Intel-gfx] [PATCH v2] drm/i915: State readout and cross-checking for dp_m2_n2 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.8 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Adding relevant read out comparison code, in check_crtc_state, for the new member of crtc_config, dp_m2_n2, which was introduced to store link_m_n values for a DP downclock mode (if available). Suggested by Daniel. v2: Changed patch title. Daniel's review comments incorporated. Added relevant state readout code for M2_N2. dp_m2_n2 comparison to be done only when high RR is not in use (This is because alternate m_n register programming will be done only when low RR is being used). Signed-off-by: Vandana Kannan Cc: Daniel Vetter --- drivers/gpu/drm/i915/intel_ddi.c | 1 + drivers/gpu/drm/i915/intel_display.c | 72 +++++++++++++++++++++++++++++++++--- drivers/gpu/drm/i915/intel_dp.c | 2 + drivers/gpu/drm/i915/intel_drv.h | 2 + 4 files changed, 72 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c index 0ad4e96..6784f0b 100644 --- a/drivers/gpu/drm/i915/intel_ddi.c +++ b/drivers/gpu/drm/i915/intel_ddi.c @@ -1587,6 +1587,7 @@ void intel_ddi_get_config(struct intel_encoder *encoder, case TRANS_DDI_MODE_SELECT_DP_MST: pipe_config->has_dp_encoder = true; intel_dp_get_m_n(intel_crtc, pipe_config); + intel_dp_get_m2_n2(intel_crtc, pipe_config); break; default: break; diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 797f01c..2e625eb 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -6670,6 +6670,34 @@ void intel_dp_get_m_n(struct intel_crtc *crtc, &pipe_config->dp_m_n); } +void intel_dp_get_m2_n2(struct intel_crtc *crtc, + struct intel_crtc_config *pipe_config) +{ + struct drm_device *dev = crtc->base.dev; + struct drm_i915_private *dev_priv = dev->dev_private; + enum transcoder transcoder = pipe_config->cpu_transcoder; + + if (INTEL_INFO(dev)->gen >= 8) { + intel_cpu_transcoder_get_m_n(crtc, transcoder, + &pipe_config->dp_m_n); + } else if (INTEL_INFO(dev)->gen > 6) { + pipe_config->dp_m2_n2.link_m = + I915_READ(PIPE_LINK_M2(transcoder)); + pipe_config->dp_m2_n2.link_n = + I915_READ(PIPE_LINK_N2(transcoder)); + pipe_config->dp_m2_n2.gmch_m = + I915_READ(PIPE_DATA_M2(transcoder)) + & ~TU_SIZE_MASK; + pipe_config->dp_m2_n2.gmch_n = + I915_READ(PIPE_DATA_N2(transcoder)); + pipe_config->dp_m2_n2.tu = + ((I915_READ(PIPE_DATA_M2(transcoder)) + & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; + } + +} + + static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc, struct intel_crtc_config *pipe_config) { @@ -9169,6 +9197,15 @@ static void intel_dump_pipe_config(struct intel_crtc *crtc, pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n, pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n, pipe_config->dp_m_n.tu); + + DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n", + pipe_config->has_dp_encoder, + pipe_config->dp_m2_n2.gmch_m, + pipe_config->dp_m2_n2.gmch_n, + pipe_config->dp_m2_n2.link_m, + pipe_config->dp_m2_n2.link_n, + pipe_config->dp_m2_n2.tu); + DRM_DEBUG_KMS("requested mode:\n"); drm_mode_debug_printmodeline(&pipe_config->requested_mode); DRM_DEBUG_KMS("adjusted mode:\n"); @@ -9533,6 +9570,14 @@ intel_pipe_config_compare(struct drm_device *dev, struct intel_crtc_config *current_config, struct intel_crtc_config *pipe_config) { + struct drm_i915_private *dev_priv = dev->dev_private; + struct intel_connector *intel_connector = dev_priv->drrs.connector; + struct intel_encoder *encoder = (intel_connector != NULL) ? + intel_attached_encoder(&intel_connector->base) : + NULL; + struct intel_dp *intel_dp = (encoder != NULL) ? + enc_to_intel_dp(&encoder->base) : NULL; + #define PIPE_CONF_CHECK_X(name) \ if (current_config->name != pipe_config->name) { \ DRM_ERROR("mismatch in " #name " " \ @@ -9583,11 +9628,28 @@ intel_pipe_config_compare(struct drm_device *dev, PIPE_CONF_CHECK_I(fdi_m_n.tu); PIPE_CONF_CHECK_I(has_dp_encoder); - PIPE_CONF_CHECK_I(dp_m_n.gmch_m); - PIPE_CONF_CHECK_I(dp_m_n.gmch_n); - PIPE_CONF_CHECK_I(dp_m_n.link_m); - PIPE_CONF_CHECK_I(dp_m_n.link_n); - PIPE_CONF_CHECK_I(dp_m_n.tu); + + + /* DP M1_N1 registers are used when DRRS is disabled or when high RR + * is used. Else, DP M2_N2 registers are used. The following check + * has been added to make sure a mismatch (if any) is displayed only + * for a real difference and not because of DRRS state. + */ + if ((dev_priv->vbt.drrs_type == DRRS_NOT_SUPPORTED) || + (dev_priv->vbt.drrs_type != DRRS_NOT_SUPPORTED && intel_dp && + intel_dp->drrs_state.refresh_rate_type == DRRS_HIGH_RR)) { + PIPE_CONF_CHECK_I(dp_m_n.gmch_m); + PIPE_CONF_CHECK_I(dp_m_n.gmch_n); + PIPE_CONF_CHECK_I(dp_m_n.link_m); + PIPE_CONF_CHECK_I(dp_m_n.link_n); + PIPE_CONF_CHECK_I(dp_m_n.tu); + } else { + PIPE_CONF_CHECK_I(dp_m2_n2.gmch_m); + PIPE_CONF_CHECK_I(dp_m2_n2.gmch_n); + PIPE_CONF_CHECK_I(dp_m2_n2.link_m); + PIPE_CONF_CHECK_I(dp_m2_n2.link_n); + PIPE_CONF_CHECK_I(dp_m2_n2.tu); + } PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay); PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal); diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 34ed143..9aa4dcd 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -1511,6 +1511,8 @@ static void intel_dp_get_config(struct intel_encoder *encoder, intel_dp_get_m_n(crtc, pipe_config); + intel_dp_get_m2_n2(crtc, pipe_config); + if (port == PORT_A) { if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ) pipe_config->port_clock = 162000; diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index d8b540b..1013f70 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -763,6 +763,8 @@ void hsw_enable_pc8(struct drm_i915_private *dev_priv); void hsw_disable_pc8(struct drm_i915_private *dev_priv); void intel_dp_get_m_n(struct intel_crtc *crtc, struct intel_crtc_config *pipe_config); +void intel_dp_get_m2_n2(struct intel_crtc *crtc, + struct intel_crtc_config *pipe_config); int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n); void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,