From patchwork Mon May 5 12:47:34 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: deepak.s@linux.intel.com X-Patchwork-Id: 4114651 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 3288EBFF02 for ; Mon, 5 May 2014 12:48:00 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 3956220200 for ; Mon, 5 May 2014 12:47:59 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 2B9FE2021A for ; Mon, 5 May 2014 12:47:58 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 9C39A6E896; Mon, 5 May 2014 05:47:57 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga03.intel.com (mga03.intel.com [143.182.124.21]) by gabe.freedesktop.org (Postfix) with ESMTP id A76E06E899 for ; Mon, 5 May 2014 05:47:56 -0700 (PDT) Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by azsmga101.ch.intel.com with ESMTP; 05 May 2014 05:47:56 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="4.97,988,1389772800"; d="scan'208";a="526183549" Received: from ds1-mobl1.gar.corp.intel.com (HELO deepaks.iind.intel.com) ([10.223.184.86]) by fmsmga001.fm.intel.com with ESMTP; 05 May 2014 05:47:54 -0700 From: deepak.s@linux.intel.com To: intel-gfx@lists.freedesktop.org Date: Mon, 5 May 2014 18:17:34 +0530 Message-Id: <1399294059-20748-6-git-send-email-deepak.s@linux.intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1399294059-20748-1-git-send-email-deepak.s@linux.intel.com> References: <1399294059-20748-1-git-send-email-deepak.s@linux.intel.com> MIME-Version: 1.0 Cc: fafael.barbalho@intel.com Subject: [Intel-gfx] [PATCH 05/10] drm/i915/chv: Streamline CHV forcewake stuff X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.8 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Deepak S Streamline the CHV forcewake functions just like was done for VLV. This will also fix a bug in accessing the common well registers, where we'd end up trying to wake up the wells too many times since we'd call force_wake_get/put twice per register access, with FORCEFAKE_ALL both times. v2: Re-factor CHV/VLV Forcewake offsets (Ben) Reviewed-by: Mika Kuoppala Signed-off-by: Ville Syrjälä Signed-off-by: Deepak S --- drivers/gpu/drm/i915/intel_uncore.c | 148 ++++++++++++++++-------------------- 1 file changed, 66 insertions(+), 82 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c index 4f1f199..d1a8c72 100644 --- a/drivers/gpu/drm/i915/intel_uncore.c +++ b/drivers/gpu/drm/i915/intel_uncore.c @@ -484,41 +484,43 @@ void assert_force_wake_inactive(struct drm_i915_private *dev_priv) #define NEEDS_FORCE_WAKE(dev_priv, reg) \ ((reg) < 0x40000 && (reg) != FORCEWAKE) +#define REG_RANGE(reg, start, end) ((reg) >= (start) && (reg) < (end)) + #define FORCEWAKE_VLV_RENDER_RANGE_OFFSET(reg) \ - (((reg) >= 0x2000 && (reg) < 0x4000) ||\ - ((reg) >= 0x5000 && (reg) < 0x8000) ||\ - ((reg) >= 0xB000 && (reg) < 0x12000) ||\ - ((reg) >= 0x2E000 && (reg) < 0x30000)) + (REG_RANGE((reg), 0x2000, 0x4000) || \ + REG_RANGE((reg), 0x5000, 0x8000) || \ + REG_RANGE((reg), 0xB000, 0x12000) || \ + REG_RANGE((reg), 0x2E000, 0x30000)) -#define FORCEWAKE_VLV_MEDIA_RANGE_OFFSET(reg)\ - (((reg) >= 0x12000 && (reg) < 0x14000) ||\ - ((reg) >= 0x22000 && (reg) < 0x24000) ||\ - ((reg) >= 0x30000 && (reg) < 0x40000)) +#define FORCEWAKE_VLV_MEDIA_RANGE_OFFSET(reg) \ + (REG_RANGE((reg), 0x12000, 0x14000) || \ + REG_RANGE((reg), 0x22000, 0x24000) || \ + REG_RANGE((reg), 0x30000, 0x40000)) #define FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg) \ - (((reg) >= 0x2000 && (reg) < 0x4000) ||\ - ((reg) >= 0x5000 && (reg) < 0x8000) ||\ - ((reg) >= 0x8300 && (reg) < 0x8500) ||\ - ((reg) >= 0xB000 && (reg) < 0xC000) ||\ - ((reg) >= 0xE000 && (reg) < 0xE800)) - -#define FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg)\ - (((reg) >= 0x8800 && (reg) < 0x8900) ||\ - ((reg) >= 0xD000 && (reg) < 0xD800) ||\ - ((reg) >= 0x12000 && (reg) < 0x14000) ||\ - ((reg) >= 0x1A000 && (reg) < 0x1C000) ||\ - ((reg) >= 0x1E800 && (reg) < 0x1EA00) ||\ - ((reg) >= 0x30000 && (reg) < 0x40000)) - -#define FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg)\ - (((reg) >= 0x4000 && (reg) < 0x5000) ||\ - ((reg) >= 0x8000 && (reg) < 0x8300) ||\ - ((reg) >= 0x8500 && (reg) < 0x8600) ||\ - ((reg) >= 0x9000 && (reg) < 0xB000) ||\ - ((reg) >= 0xC000 && (reg) < 0xc800) ||\ - ((reg) >= 0xF000 && (reg) < 0x10000) ||\ - ((reg) >= 0x14000 && (reg) < 0x14400) ||\ - ((reg) >= 0x22000 && (reg) < 0x24000)) + (REG_RANGE((reg), 0x2000, 0x4000) || \ + REG_RANGE((reg), 0x5000, 0x8000) || \ + REG_RANGE((reg), 0x8300, 0x8500) || \ + REG_RANGE((reg), 0xB000, 0xC000) || \ + REG_RANGE((reg), 0xE000, 0xE800)) + +#define FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg) \ + (REG_RANGE((reg), 0x8800, 0x8900) || \ + REG_RANGE((reg), 0xD000, 0xD800) || \ + REG_RANGE((reg), 0x12000, 0x14000) || \ + REG_RANGE((reg), 0x1A000, 0x1C000) || \ + REG_RANGE((reg), 0x1E800, 0x1EA00) || \ + REG_RANGE((reg), 0x30000, 0x40000)) + +#define FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg) \ + (REG_RANGE((reg), 0x4000, 0x5000) || \ + REG_RANGE((reg), 0x8000, 0x8300) || \ + REG_RANGE((reg), 0x8500, 0x8600) || \ + REG_RANGE((reg), 0x9000, 0xB000) || \ + REG_RANGE((reg), 0xC000, 0xC800) || \ + REG_RANGE((reg), 0xF000, 0x10000) || \ + REG_RANGE((reg), 0x14000, 0x14400) || \ + REG_RANGE((reg), 0x22000, 0x24000)) static void ilk_dummy_write(struct drm_i915_private *dev_priv) @@ -618,33 +620,23 @@ static u##x \ chv_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \ unsigned fwengine = 0; \ REG_READ_HEADER(x); \ - if (FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg)) \ - fwengine = FORCEWAKE_RENDER; \ - else if (FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg)) \ - fwengine = FORCEWAKE_MEDIA; \ - else if (FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg)) \ - fwengine = FORCEWAKE_ALL; \ - if (FORCEWAKE_RENDER & fwengine) { \ - if (dev_priv->uncore.fw_rendercount++ == 0) \ - (dev_priv)->uncore.funcs.force_wake_get(dev_priv, \ - fwengine); \ - } \ - if (FORCEWAKE_MEDIA & fwengine) { \ - if (dev_priv->uncore.fw_mediacount++ == 0) \ - (dev_priv)->uncore.funcs.force_wake_get(dev_priv, \ - fwengine); \ + if (FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg)) { \ + if (dev_priv->uncore.fw_rendercount == 0) \ + fwengine = FORCEWAKE_RENDER; \ + } else if (FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg)) { \ + if (dev_priv->uncore.fw_mediacount == 0) \ + fwengine = FORCEWAKE_MEDIA; \ + } else if (FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg)) { \ + if (dev_priv->uncore.fw_rendercount == 0) \ + fwengine |= FORCEWAKE_RENDER; \ + if (dev_priv->uncore.fw_mediacount == 0) \ + fwengine |= FORCEWAKE_MEDIA; \ } \ + if (fwengine) \ + dev_priv->uncore.funcs.force_wake_get(dev_priv, fwengine); \ val = __raw_i915_read##x(dev_priv, reg); \ - if (FORCEWAKE_RENDER & fwengine) { \ - if (--dev_priv->uncore.fw_rendercount == 0) \ - (dev_priv)->uncore.funcs.force_wake_put(dev_priv, \ - fwengine); \ - } \ - if (FORCEWAKE_MEDIA & fwengine) { \ - if (--dev_priv->uncore.fw_mediacount == 0) \ - (dev_priv)->uncore.funcs.force_wake_put(dev_priv, \ - fwengine); \ - } \ + if (fwengine) \ + dev_priv->uncore.funcs.force_wake_put(dev_priv, fwengine); \ REG_READ_FOOTER; \ } @@ -778,35 +770,27 @@ gen8_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace static void \ chv_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \ unsigned fwengine = 0; \ - bool __needs_put = !is_gen8_shadowed(dev_priv, reg); \ + bool shadowed = is_gen8_shadowed(dev_priv, reg); \ REG_WRITE_HEADER; \ - if (FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg)) \ - fwengine = FORCEWAKE_RENDER; \ - else if (FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg)) \ - fwengine = FORCEWAKE_MEDIA; \ - else if (FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg)) \ - fwengine = FORCEWAKE_ALL; \ - if (__needs_put && (FORCEWAKE_RENDER & fwengine)) { \ - if (dev_priv->uncore.fw_rendercount++ == 0) \ - (dev_priv)->uncore.funcs.force_wake_get(dev_priv, \ - fwengine); \ - } \ - if (__needs_put && (FORCEWAKE_MEDIA & fwengine)) { \ - if (dev_priv->uncore.fw_mediacount++ == 0) \ - (dev_priv)->uncore.funcs.force_wake_get(dev_priv, \ - fwengine); \ + if (!shadowed) { \ + if (FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg)) { \ + if (dev_priv->uncore.fw_rendercount == 0) \ + fwengine = FORCEWAKE_RENDER; \ + } else if (FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg)) { \ + if (dev_priv->uncore.fw_mediacount == 0) \ + fwengine = FORCEWAKE_MEDIA; \ + } else if (FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg)) { \ + if (dev_priv->uncore.fw_rendercount == 0) \ + fwengine |= FORCEWAKE_RENDER; \ + if (dev_priv->uncore.fw_mediacount == 0) \ + fwengine |= FORCEWAKE_MEDIA; \ + } \ } \ + if (fwengine) \ + dev_priv->uncore.funcs.force_wake_get(dev_priv, fwengine); \ __raw_i915_write##x(dev_priv, reg, val); \ - if (__needs_put && (FORCEWAKE_RENDER & fwengine)) { \ - if (--dev_priv->uncore.fw_rendercount == 0) \ - (dev_priv)->uncore.funcs.force_wake_put(dev_priv, \ - fwengine); \ - } \ - if (__needs_put && (FORCEWAKE_MEDIA & fwengine)) { \ - if (--dev_priv->uncore.fw_mediacount == 0) \ - (dev_priv)->uncore.funcs.force_wake_put(dev_priv, \ - fwengine); \ - } \ + if (fwengine) \ + dev_priv->uncore.funcs.force_wake_put(dev_priv, fwengine); \ REG_WRITE_FOOTER; \ }