From patchwork Mon May 5 12:47:35 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: deepak.s@linux.intel.com X-Patchwork-Id: 4114661 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 646B5BFF02 for ; Mon, 5 May 2014 12:48:02 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 5ADD020218 for ; Mon, 5 May 2014 12:48:01 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 57B0420200 for ; Mon, 5 May 2014 12:48:00 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id C564A6E898; Mon, 5 May 2014 05:47:59 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga03.intel.com (mga03.intel.com [143.182.124.21]) by gabe.freedesktop.org (Postfix) with ESMTP id 6B3FD6E898 for ; Mon, 5 May 2014 05:47:58 -0700 (PDT) Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by azsmga101.ch.intel.com with ESMTP; 05 May 2014 05:47:58 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="4.97,988,1389772800"; d="scan'208";a="526183572" Received: from ds1-mobl1.gar.corp.intel.com (HELO deepaks.iind.intel.com) ([10.223.184.86]) by fmsmga001.fm.intel.com with ESMTP; 05 May 2014 05:47:56 -0700 From: deepak.s@linux.intel.com To: intel-gfx@lists.freedesktop.org Date: Mon, 5 May 2014 18:17:35 +0530 Message-Id: <1399294059-20748-7-git-send-email-deepak.s@linux.intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1399294059-20748-1-git-send-email-deepak.s@linux.intel.com> References: <1399294059-20748-1-git-send-email-deepak.s@linux.intel.com> Cc: Daniel Vetter , fafael.barbalho@intel.com Subject: [Intel-gfx] [PATCH 06/10] drm/i915/chv: Enable RPS (Turbo) for Cherryview X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.8 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Deepak S v2: Disable media turbo and Add DOWN_IDLE_AVG support (Ville) v3: Mass rename of the dev_priv->rps variables in upstream. v4: Rebase against latest code. (Deepak) Signed-off-by: Deepak S Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/drm/i915/i915_reg.h | 10 ++++ drivers/gpu/drm/i915/intel_pm.c | 95 ++++++++++++++++++++++++++++++++++- drivers/gpu/drm/i915/intel_sideband.c | 15 ++++++ 4 files changed, 120 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 5f4f631..e70a9f0 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -2552,6 +2552,7 @@ int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val) u32 vlv_punit_read(struct drm_i915_private *dev_priv, u8 addr); void vlv_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 val); u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr); +u32 chv_nc_read(struct drm_i915_private *dev_priv, u8 addr); u32 vlv_gpio_nc_read(struct drm_i915_private *dev_priv, u32 reg); void vlv_gpio_nc_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg); diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index b4074fd..3ff34c4 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -475,6 +475,7 @@ #define VLV_IOSF_DATA (VLV_DISPLAY_BASE + 0x2104) #define VLV_IOSF_ADDR (VLV_DISPLAY_BASE + 0x2108) +#define CHV_IOSF_PORT_NC 0x04 /* See configdb bunit SB addr map */ #define BUNIT_REG_BISOC 0x11 @@ -520,6 +521,14 @@ enum punit_power_well { #define PUNIT_FUSE_BUS2 0xf6 /* bits 47:40 */ #define PUNIT_FUSE_BUS1 0xf5 /* bits 55:48 */ +#define CHV_IOSF_NC_FB_GFX_FREQ_FUSE 0xdb +#define CHV_FB_GFX_MAX_FREQ_FUSE_SHIFT 16 +#define CHV_FB_GFX_MAX_FREQ_FUSE_MASK 0xff + +#define CHV_IOSF_NC_FB_GFX_RPE_FUSE 0xdf +#define CHV_FB_RPE_FREQ_SHIFT 8 +#define CHV_FB_RPE_FREQ_MASK 0xff + #define IOSF_NC_FB_GFX_FREQ_FUSE 0x1c #define FB_GFX_MAX_FREQ_FUSE_SHIFT 3 #define FB_GFX_MAX_FREQ_FUSE_MASK 0x000007f8 @@ -747,6 +756,7 @@ enum punit_power_well { #define SANDYBRIDGE_FENCE_PITCH_SHIFT 32 #define GEN7_FENCE_MAX_PITCH_VAL 0x0800 + /* control register for cpu gtt access */ #define TILECTL 0x101000 #define TILECTL_SWZCTL (1 << 0) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index f0359b6..dedbdf3 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -3690,6 +3690,38 @@ void gen6_update_ring_freq(struct drm_device *dev) mutex_unlock(&dev_priv->rps.hw_lock); } +int cherryview_rps_max_freq(struct drm_i915_private *dev_priv) +{ + u32 val, rp0; + + val = chv_nc_read(dev_priv, CHV_IOSF_NC_FB_GFX_FREQ_FUSE); + + rp0 = (val >> CHV_FB_GFX_MAX_FREQ_FUSE_SHIFT) & + CHV_FB_GFX_MAX_FREQ_FUSE_MASK; + + return rp0; +} + +static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv) +{ + u32 val, rpe; + + val = chv_nc_read(dev_priv, CHV_IOSF_NC_FB_GFX_RPE_FUSE); + rpe = (val >> CHV_FB_RPE_FREQ_SHIFT) & CHV_FB_RPE_FREQ_MASK; + + return rpe; +} + +int cherryview_rps_min_freq(struct drm_i915_private *dev_priv) +{ + u32 val, rpn; + + val = chv_nc_read(dev_priv, CHV_IOSF_NC_FB_GFX_FREQ_FUSE); + rpn = (val >> CHV_FB_RPE_FREQ_SHIFT) & CHV_FB_RPE_FREQ_MASK; + + return rpn; +} + int valleyview_rps_max_freq(struct drm_i915_private *dev_priv) { u32 val, rp0; @@ -3847,7 +3879,36 @@ static void valleyview_init_gt_powersave(struct drm_device *dev) static void cherryview_init_gt_powersave(struct drm_device *dev) { + struct drm_i915_private *dev_priv = dev->dev_private; + cherryview_setup_pctx(dev); + + mutex_lock(&dev_priv->rps.hw_lock); + + dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv); + dev_priv->rps.rp0_freq = dev_priv->rps.max_freq; + DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n", + vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq), + dev_priv->rps.max_freq); + + dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv); + DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n", + vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq), + dev_priv->rps.efficient_freq); + + dev_priv->rps.min_freq = cherryview_rps_min_freq(dev_priv); + DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n", + vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq), + dev_priv->rps.min_freq); + + /* Preserve min/max settings in case of re-init */ + if (dev_priv->rps.max_freq_softlimit == 0) + dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq; + + if (dev_priv->rps.min_freq_softlimit == 0) + dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq; + + mutex_unlock(&dev_priv->rps.hw_lock); } static void valleyview_cleanup_gt_powersave(struct drm_device *dev) @@ -3859,7 +3920,7 @@ static void cherryview_enable_rps(struct drm_device *dev) { struct drm_i915_private *dev_priv = dev->dev_private; struct intel_ring_buffer *ring; - u32 gtfifodbg, rc6_mode = 0, pcbr; + u32 gtfifodbg, val, rc6_mode = 0, pcbr; int i; WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); @@ -3908,6 +3969,38 @@ static void cherryview_enable_rps(struct drm_device *dev) I915_WRITE(GEN6_RC_CONTROL, rc6_mode); + /* 4 Program defaults and thresholds for RPS*/ + I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400); + I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000); + I915_WRITE(GEN6_RP_UP_EI, 66000); + I915_WRITE(GEN6_RP_DOWN_EI, 350000); + + I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10); + + /* 5: Enable RPS */ + I915_WRITE(GEN6_RP_CONTROL, + GEN6_RP_MEDIA_HW_NORMAL_MODE | + GEN6_RP_MEDIA_IS_GFX | + GEN6_RP_ENABLE | + GEN6_RP_UP_BUSY_AVG | + GEN6_RP_DOWN_IDLE_AVG); + + val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); + + DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & 0x10 ? "yes" : "no"); + DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val); + + dev_priv->rps.cur_freq = (val >> 8) & 0xff; + DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n", + vlv_gpu_freq(dev_priv, dev_priv->rps.cur_freq), + dev_priv->rps.cur_freq); + + DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n", + vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq), + dev_priv->rps.efficient_freq); + + valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq); + gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL); } diff --git a/drivers/gpu/drm/i915/intel_sideband.c b/drivers/gpu/drm/i915/intel_sideband.c index b1a5514..8f6904d 100644 --- a/drivers/gpu/drm/i915/intel_sideband.c +++ b/drivers/gpu/drm/i915/intel_sideband.c @@ -106,6 +106,21 @@ void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val) PUNIT_OPCODE_REG_WRITE, reg, &val); } +u32 chv_nc_read(struct drm_i915_private *dev_priv, u8 addr) +{ + u32 val = 0; + + WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); + + mutex_lock(&dev_priv->dpio_lock); + vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), CHV_IOSF_PORT_NC, + PUNIT_OPCODE_REG_READ, addr, &val); + mutex_unlock(&dev_priv->dpio_lock); + + return val; +} + + u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr) { u32 val = 0;