From patchwork Sat May 10 03:59:25 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ben Widawsky X-Patchwork-Id: 4146261 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id CD8809F387 for ; Sat, 10 May 2014 04:01:42 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id E9E7D200B4 for ; Sat, 10 May 2014 04:01:41 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id EFCB12021B for ; Sat, 10 May 2014 04:01:39 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 88F8F6F08F; Fri, 9 May 2014 21:01:39 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail.bwidawsk.net (bwidawsk.net [166.78.191.112]) by gabe.freedesktop.org (Postfix) with ESMTP id B50F36F08E for ; Fri, 9 May 2014 21:01:38 -0700 (PDT) Received: by mail.bwidawsk.net (Postfix, from userid 5001) id BBD4B580AE; Fri, 9 May 2014 21:01:37 -0700 (PDT) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Spam-Level: X-Spam-Status: No, score=-4.8 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 Received: from ironside.intel.com (c-24-21-100-90.hsd1.or.comcast.net [24.21.100.90]) by mail.bwidawsk.net (Postfix) with ESMTPSA id 1322A58089; Fri, 9 May 2014 21:00:19 -0700 (PDT) From: Ben Widawsky To: Intel GFX Date: Fri, 9 May 2014 20:59:25 -0700 Message-Id: <1399694391-3935-31-git-send-email-benjamin.widawsky@intel.com> X-Mailer: git-send-email 1.9.2 In-Reply-To: <1399694391-3935-1-git-send-email-benjamin.widawsky@intel.com> References: <1399694391-3935-1-git-send-email-benjamin.widawsky@intel.com> Cc: Ben Widawsky , Ben Widawsky Subject: [Intel-gfx] [PATCH 30/56] drm/i915/bdw: Use dynamic allocation idioms on free X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP The page directory freer is left here for now as it's still useful given that GEN8 still preallocates. Once the allocation functions are broken up into more discrete chunks, we'll follow suit and destroy this leftover piece. comments Signed-off-by: Ben Widawsky --- drivers/gpu/drm/i915/i915_gem_gtt.c | 45 ++++++++++++++++++++++++------------- drivers/gpu/drm/i915/i915_gem_gtt.h | 26 +++++++++++++++++++++ 2 files changed, 55 insertions(+), 16 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c index 68cc1ab..14aae05 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.c +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c @@ -531,27 +531,40 @@ static void gen8_ppgtt_insert_entries(struct i915_address_space *vm, } } -static void gen8_free_page_tables(struct i915_pagedir *pd, struct drm_device *dev) +static void gen8_teardown_va_range(struct i915_address_space *vm, + uint64_t start, uint64_t length) { - int i; - - if (!pd->page) - return; - - for (i = 0; i < I915_PDES_PER_PD; i++) { - free_pt_single(pd->page_tables[i], dev); - pd->page_tables[i] = NULL; + struct i915_hw_ppgtt *ppgtt = + container_of(vm, struct i915_hw_ppgtt, base); + struct i915_pagedir *pd; + struct i915_pagetab *pt; + uint64_t temp; + uint32_t pdpe, pde; + + gen8_for_each_pdpe(pd, &ppgtt->pdp, start, length, temp, pdpe) { + uint64_t pd_len = gen8_clamp_pd(start, length); + uint64_t pd_start = start; + gen8_for_each_pde(pt, pd, pd_start, pd_len, temp, pde) { + free_pt_single(pt, vm->dev); + } + free_pd_single(pd, vm->dev); } } -static void gen8_ppgtt_free(struct i915_hw_ppgtt *ppgtt) +/* This function will die soon */ +static void gen8_free_full_pagedir(struct i915_hw_ppgtt *ppgtt, int i) { - int i; + gen8_teardown_va_range(&ppgtt->base, + i << GEN8_PDPE_SHIFT, + (1 << GEN8_PDPE_SHIFT)); +} - for (i = 0; i < ppgtt->num_pd_pages; i++) { - gen8_free_page_tables(ppgtt->pdp.pagedirs[i], ppgtt->base.dev); - free_pd_single(ppgtt->pdp.pagedirs[i], ppgtt->base.dev); - } +static void gen8_ppgtt_free(struct i915_hw_ppgtt *ppgtt) +{ + trace_i915_va_teardown(&ppgtt->base, + ppgtt->base.start, ppgtt->base.total); + gen8_teardown_va_range(&ppgtt->base, + ppgtt->base.start, ppgtt->base.total); } static void gen8_ppgtt_cleanup(struct i915_address_space *vm) @@ -580,7 +593,7 @@ static int gen8_ppgtt_allocate_page_tables(struct i915_hw_ppgtt *ppgtt) unwind_out: while (i--) - gen8_free_page_tables(ppgtt->pdp.pagedirs[i], ppgtt->base.dev); + gen8_free_full_pagedir(ppgtt, i); return -ENOMEM; } diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h b/drivers/gpu/drm/i915/i915_gem_gtt.h index d8a990e..f81b26a 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.h +++ b/drivers/gpu/drm/i915/i915_gem_gtt.h @@ -395,6 +395,32 @@ static inline size_t gen6_pde_count(uint32_t addr, uint32_t length) return i915_pde_count(addr, length, GEN6_PDE_SHIFT); } +#define gen8_for_each_pde(pt, pd, start, length, temp, iter) \ + for (iter = gen8_pde_index(start), pt = (pd)->page_tables[iter]; \ + length > 0 && iter < I915_PDES_PER_PD; \ + pt = (pd)->page_tables[++iter], \ + temp = ALIGN(start+1, 1 << GEN8_PDE_SHIFT) - start, \ + temp = min(temp, length), \ + start += temp, length -= temp) + +#define gen8_for_each_pdpe(pd, pdp, start, length, temp, iter) \ + for (iter = gen8_pdpe_index(start), pd = (pdp)->pagedirs[iter]; \ + length > 0 && iter < GEN8_LEGACY_PDPES; \ + pd = (pdp)->pagedirs[++iter], \ + temp = ALIGN(start+1, 1 << GEN8_PDPE_SHIFT) - start, \ + temp = min(temp, length), \ + start += temp, length -= temp) + +/* Clamp length to the next pagedir boundary */ +static inline uint64_t gen8_clamp_pd(uint64_t start, uint64_t length) +{ + uint64_t next_pd = ALIGN(start + 1, 1 << GEN8_PDPE_SHIFT); + if (next_pd > (start + length)) + return length; + + return next_pd - start; +} + static inline uint32_t gen8_pte_index(uint64_t address) { return i915_pte_index(address, GEN8_PDE_SHIFT);