From patchwork Fri May 23 20:16:42 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jesse Barnes X-Patchwork-Id: 4235801 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 602CD9F32B for ; Fri, 23 May 2014 20:17:01 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 89D412034B for ; Fri, 23 May 2014 20:17:00 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 7A173203B5 for ; Fri, 23 May 2014 20:16:59 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 978906EECD; Fri, 23 May 2014 13:16:58 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from gproxy4-pub.mail.unifiedlayer.com (gproxy4-pub.mail.unifiedlayer.com [69.89.23.142]) by gabe.freedesktop.org (Postfix) with SMTP id 4B7BC6E1F7 for ; Fri, 23 May 2014 13:16:57 -0700 (PDT) Received: (qmail 29947 invoked by uid 0); 23 May 2014 20:16:57 -0000 Received: from unknown (HELO cmgw4) (10.0.90.85) by gproxy4.mail.unifiedlayer.com with SMTP; 23 May 2014 20:16:57 -0000 Received: from box514.bluehost.com ([74.220.219.114]) by cmgw4 with id 5YGr1o0192UhLwi01YGuXY; Fri, 23 May 2014 14:16:57 -0600 X-Authority-Analysis: v=2.1 cv=CpMsLBID c=1 sm=1 tr=0 a=9W6Fsu4pMcyimqnCr1W0/w==:117 a=9W6Fsu4pMcyimqnCr1W0/w==:17 a=cNaOj0WVAAAA:8 a=f5113yIGAAAA:8 a=H_gm9cpEJEwA:10 a=3ROhxo7VqVMA:10 a=TBVoxVdAAAAA:8 a=GhZ5P8ky69gA:10 a=noBwr2J6l1kA:10 a=pSxdiv-P5wnnXaHuGIsA:9 a=rW6DTWptwo0A:10 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=virtuousgeek.org; s=default; h=References:In-Reply-To:Message-Id:Date:Subject:To:From; bh=lTCT6afJQ+VjPK4VwsUciNs/X2KRoqmFJXCpwo7HfCc=; b=YPY8+oyBG89zSj4sIJP7gHyFjrQoxmFG6wH/FfbaVxDB32tyZLBu9dhqXHmiaXmqDkeMSacJ/Zls6xRp4You6hIorjnMSbBuDtjg9sHUtcP+IJcBuE712+dZlnmzXOEo; Received: from [67.161.37.189] (port=49075 helo=localhost.localdomain) by box514.bluehost.com with esmtpsa (TLSv1.2:DHE-RSA-AES256-GCM-SHA384:256) (Exim 4.82) (envelope-from ) id 1Wnvtb-0000KX-H6 for intel-gfx@lists.freedesktop.org; Fri, 23 May 2014 14:16:51 -0600 From: Jesse Barnes To: intel-gfx@lists.freedesktop.org Date: Fri, 23 May 2014 13:16:42 -0700 Message-Id: <1400876205-12997-3-git-send-email-jbarnes@virtuousgeek.org> X-Mailer: git-send-email 1.8.4.2 In-Reply-To: <1400876205-12997-1-git-send-email-jbarnes@virtuousgeek.org> References: <1400876205-12997-1-git-send-email-jbarnes@virtuousgeek.org> X-Identified-User: {10642:box514.bluehost.com:virtuous:virtuousgeek.org} {sentby:smtp auth 67.161.37.189 authed with jbarnes@virtuousgeek.org} Subject: [Intel-gfx] [PATCH 3/6] drm/i915/vlv: move CRI refclk enable into __vlv_set_power_well X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.7 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED,RP_MATCHES_RCVD,T_DKIM_INVALID,UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This needs to be done before we power back on the CMN_BC well so the PHY can calibrate properly. Signed-off-by: Jesse Barnes --- drivers/gpu/drm/i915/intel_display.c | 8 -------- drivers/gpu/drm/i915/intel_pm.c | 11 +++++++++++ 2 files changed, 11 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index bdb4624..369cd1e 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -1477,14 +1477,6 @@ static void intel_reset_dpio(struct drm_device *dev) if (!IS_VALLEYVIEW(dev)) return; - /* - * Enable the CRI clock source so we can get at the display and the - * reference clock for VGA hotplug / manual detection. - */ - I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) | - DPLL_REFA_CLK_ENABLE_VLV | - DPLL_INTEGRATED_CRI_CLK_VLV); - if (IS_CHERRYVIEW(dev)) { enum dpio_phy phy; u32 val; diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 8f7dbb9..e8f0c85 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -5731,6 +5731,17 @@ void __vlv_set_power_well(struct drm_i915_private *dev_priv, u32 state; u32 ctrl; + if (power_well_id == PUNIT_POWER_WELL_DPIO_CMN_BC && enable) { + /* + * Enable the CRI clock source so we can get at the display + * and the reference clock for VGA hotplug / manual detection. + */ + I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) | + DPLL_REFA_CLK_ENABLE_VLV | + DPLL_INTEGRATED_CRI_CLK_VLV); + udelay(1); /* >10ns for cmnreset, >0ns for sidereset */ + } + mask = PUNIT_PWRGT_MASK(power_well_id); state = enable ? PUNIT_PWRGT_PWR_ON(power_well_id) : PUNIT_PWRGT_PWR_GATE(power_well_id);