From patchwork Fri May 23 20:16:44 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jesse Barnes X-Patchwork-Id: 4235821 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id B2FC7BF90B for ; Fri, 23 May 2014 20:17:04 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id C28A9203B5 for ; Fri, 23 May 2014 20:17:03 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id F3B5C20351 for ; Fri, 23 May 2014 20:17:02 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 998416EE9E; Fri, 23 May 2014 13:17:02 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from gproxy4-pub.mail.unifiedlayer.com (gproxy4-pub.mail.unifiedlayer.com [69.89.23.142]) by gabe.freedesktop.org (Postfix) with SMTP id D623C6EEC3 for ; Fri, 23 May 2014 13:16:58 -0700 (PDT) Received: (qmail 30070 invoked by uid 0); 23 May 2014 20:16:58 -0000 Received: from unknown (HELO cmgw2) (10.0.90.83) by gproxy4.mail.unifiedlayer.com with SMTP; 23 May 2014 20:16:58 -0000 Received: from box514.bluehost.com ([74.220.219.114]) by cmgw2 with id 5YGr1o00U2UhLwi01YGuvZ; Fri, 23 May 2014 14:16:57 -0600 X-Authority-Analysis: v=2.1 cv=Q9RBveGa c=1 sm=1 tr=0 a=9W6Fsu4pMcyimqnCr1W0/w==:117 a=9W6Fsu4pMcyimqnCr1W0/w==:17 a=cNaOj0WVAAAA:8 a=f5113yIGAAAA:8 a=SyI_N41-O6wA:10 a=3ROhxo7VqVMA:10 a=TBVoxVdAAAAA:8 a=GhZ5P8ky69gA:10 a=noBwr2J6l1kA:10 a=LsM87G-d-cBykdspepAA:9 a=rW6DTWptwo0A:10 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=virtuousgeek.org; s=default; h=References:In-Reply-To:Message-Id:Date:Subject:To:From; bh=c4aaJCv3AZ+HMScCpsElAq12JnkEbM04Jgc6Fif8U1U=; b=sibGtItkrOELyagQvEa9haK7sP85bpUXKxC7Qb7Dj7XdBeTpKqCMGMCbRv7Q9Ip1FcPZsvf4tNpS0gNVu12leB9zx/fv9zxmYSWCrZ1M6RxLAPXDcqkaF8SjrYORdgEI; Received: from [67.161.37.189] (port=49075 helo=localhost.localdomain) by box514.bluehost.com with esmtpsa (TLSv1.2:DHE-RSA-AES256-GCM-SHA384:256) (Exim 4.82) (envelope-from ) id 1Wnvtc-0000KX-0c for intel-gfx@lists.freedesktop.org; Fri, 23 May 2014 14:16:52 -0600 From: Jesse Barnes To: intel-gfx@lists.freedesktop.org Date: Fri, 23 May 2014 13:16:44 -0700 Message-Id: <1400876205-12997-5-git-send-email-jbarnes@virtuousgeek.org> X-Mailer: git-send-email 1.8.4.2 In-Reply-To: <1400876205-12997-1-git-send-email-jbarnes@virtuousgeek.org> References: <1400876205-12997-1-git-send-email-jbarnes@virtuousgeek.org> X-Identified-User: {10642:box514.bluehost.com:virtuous:virtuousgeek.org} {sentby:smtp auth 67.161.37.189 authed with jbarnes@virtuousgeek.org} Subject: [Intel-gfx] [PATCH 5/6] drm/i915/vlv: move DPIO common reset de-assert into __vlv_set_power_well X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.7 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED,RP_MATCHES_RCVD,T_DKIM_INVALID,UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP We need to do this anytime we power gate the DPIO common well. Signed-off-by: Jesse Barnes --- drivers/gpu/drm/i915/intel_display.c | 13 ------------ drivers/gpu/drm/i915/intel_pm.c | 39 +++++++++++++++++++++++++++--------- 2 files changed, 30 insertions(+), 22 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 369cd1e..bfa1fc7 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -1518,19 +1518,6 @@ static void intel_reset_dpio(struct drm_device *dev) false); __vlv_set_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC, true); - - /* - * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx - - * 6. De-assert cmn_reset/side_reset. Same as VLV X0. - * a. GUnit 0x2110 bit[0] set to 1 (def 0) - * b. The other bits such as sfr settings / modesel may all - * be set to 0. - * - * This should only be done on init and resume from S3 with - * both PLLs disabled, or we risk losing DPIO and PLL - * synchronization. - */ - I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST); } } diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index fb7e23e..948a4aa 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -5731,15 +5731,22 @@ void __vlv_set_power_well(struct drm_i915_private *dev_priv, u32 state; u32 ctrl; - if (power_well_id == PUNIT_POWER_WELL_DPIO_CMN_BC && enable) { - /* - * Enable the CRI clock source so we can get at the display - * and the reference clock for VGA hotplug / manual detection. - */ - I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) | - DPLL_REFA_CLK_ENABLE_VLV | - DPLL_INTEGRATED_CRI_CLK_VLV); - udelay(1); /* >10ns for cmnreset, >0ns for sidereset */ + if (power_well_id == PUNIT_POWER_WELL_DPIO_CMN_BC) { + if (enable) { + /* + * Enable the CRI clock source so we can get at the + * display and the reference clock for VGA + * hotplug / manual detection. + */ + I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) | + DPLL_REFA_CLK_ENABLE_VLV | + DPLL_INTEGRATED_CRI_CLK_VLV); + udelay(1); /* >10ns for cmnreset, >0ns for sidereset */ + } else { + /* Assert common reset */ + I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) & + ~DPIO_CMNRST); + } } mask = PUNIT_PWRGT_MASK(power_well_id); @@ -5768,6 +5775,20 @@ void __vlv_set_power_well(struct drm_i915_private *dev_priv, out: mutex_unlock(&dev_priv->rps.hw_lock); + + /* + * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx - + * 6. De-assert cmn_reset/side_reset. Same as VLV X0. + * a. GUnit 0x2110 bit[0] set to 1 (def 0) + * b. The other bits such as sfr settings / modesel may all + * be set to 0. + * + * This should only be done on init and resume from S3 with + * both PLLs disabled, or we risk losing DPIO and PLL + * synchronization. + */ + if (power_well_id == PUNIT_POWER_WELL_DPIO_CMN_BC && enable) + I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST); } static void vlv_set_power_well(struct drm_i915_private *dev_priv,