From patchwork Fri May 23 20:16:45 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jesse Barnes X-Patchwork-Id: 4235831 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id F0DA5BF90B for ; Fri, 23 May 2014 20:17:06 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 2C52320351 for ; Fri, 23 May 2014 20:17:06 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 4EA742034B for ; Fri, 23 May 2014 20:17:05 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id F08B56EEB1; Fri, 23 May 2014 13:17:04 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from gproxy5-pub.mail.unifiedlayer.com (gproxy5-pub.mail.unifiedlayer.com [67.222.38.55]) by gabe.freedesktop.org (Postfix) with SMTP id 9325B6EE9E for ; Fri, 23 May 2014 13:16:58 -0700 (PDT) Received: (qmail 7109 invoked by uid 0); 23 May 2014 20:16:56 -0000 Received: from unknown (HELO CMOut01) (10.0.90.82) by gproxy5.mail.unifiedlayer.com with SMTP; 23 May 2014 20:16:56 -0000 Received: from box514.bluehost.com ([74.220.219.114]) by CMOut01 with id 5YGs1o00k2UhLwi01YGvcA; Fri, 23 May 2014 14:16:56 -0600 X-Authority-Analysis: v=2.1 cv=EOmVjTpC c=1 sm=1 tr=0 a=9W6Fsu4pMcyimqnCr1W0/w==:117 a=9W6Fsu4pMcyimqnCr1W0/w==:17 a=cNaOj0WVAAAA:8 a=f5113yIGAAAA:8 a=7cJQpqrc3yoA:10 a=3ROhxo7VqVMA:10 a=TBVoxVdAAAAA:8 a=GhZ5P8ky69gA:10 a=noBwr2J6l1kA:10 a=wqcgi8zOvq3VEDsIgkkA:9 a=rW6DTWptwo0A:10 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=virtuousgeek.org; s=default; h=References:In-Reply-To:Message-Id:Date:Subject:To:From; bh=9VX+ako135s9z86X8je9VQASl3s7l/q6yJLaQJAbaxI=; b=bA5eI+gcMZ3DU3aytQN84RMSrztr0HNPybmr2s7rDcznPqk36QXgiR+/vaAoDlzuzsdIzRdbORcPm2Phdzd06bXiJnhSehlFQWmT3GlhiBrB7qsHcsYB4gZ9ATALjr12; Received: from [67.161.37.189] (port=49075 helo=localhost.localdomain) by box514.bluehost.com with esmtpsa (TLSv1.2:DHE-RSA-AES256-GCM-SHA384:256) (Exim 4.82) (envelope-from ) id 1Wnvtc-0000KX-9x for intel-gfx@lists.freedesktop.org; Fri, 23 May 2014 14:16:52 -0600 From: Jesse Barnes To: intel-gfx@lists.freedesktop.org Date: Fri, 23 May 2014 13:16:45 -0700 Message-Id: <1400876205-12997-6-git-send-email-jbarnes@virtuousgeek.org> X-Mailer: git-send-email 1.8.4.2 In-Reply-To: <1400876205-12997-1-git-send-email-jbarnes@virtuousgeek.org> References: <1400876205-12997-1-git-send-email-jbarnes@virtuousgeek.org> X-Identified-User: {10642:box514.bluehost.com:virtuous:virtuousgeek.org} {sentby:smtp auth 67.161.37.189 authed with jbarnes@virtuousgeek.org} Subject: [Intel-gfx] [PATCH 6/6] drm/i915/vlv: add pll assertion when disabling DPIO common well X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.7 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED,RP_MATCHES_RCVD,T_DKIM_INVALID,UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP When doing this, all PLLs should be disabled. Signed-off-by: Jesse Barnes --- drivers/gpu/drm/i915/intel_pm.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 948a4aa..452518f 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -5727,9 +5727,11 @@ static bool i9xx_always_on_power_well_enabled(struct drm_i915_private *dev_priv, void __vlv_set_power_well(struct drm_i915_private *dev_priv, enum punit_power_well power_well_id, bool enable) { + struct drm_device *dev = dev_priv->dev; u32 mask; u32 state; u32 ctrl; + enum pipe pipe; if (power_well_id == PUNIT_POWER_WELL_DPIO_CMN_BC) { if (enable) { @@ -5743,6 +5745,8 @@ void __vlv_set_power_well(struct drm_i915_private *dev_priv, DPLL_INTEGRATED_CRI_CLK_VLV); udelay(1); /* >10ns for cmnreset, >0ns for sidereset */ } else { + for_each_pipe(pipe) + assert_pll_disabled(dev_priv, pipe); /* Assert common reset */ I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) & ~DPIO_CMNRST);