From patchwork Thu May 29 09:40:15 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: sourab.gupta@intel.com X-Patchwork-Id: 4263681 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 86BB9BF90B for ; Thu, 29 May 2014 09:39:42 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id B332020303 for ; Thu, 29 May 2014 09:39:41 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id C3BB5202F8 for ; Thu, 29 May 2014 09:39:40 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 648AF6E997; Thu, 29 May 2014 02:39:40 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga03.intel.com (mga03.intel.com [143.182.124.21]) by gabe.freedesktop.org (Postfix) with ESMTP id C72FC6E997 for ; Thu, 29 May 2014 02:39:34 -0700 (PDT) Received: from azsmga001.ch.intel.com ([10.2.17.19]) by azsmga101.ch.intel.com with ESMTP; 29 May 2014 02:39:34 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="4.98,933,1392192000"; d="scan'208";a="438473380" Received: from sourabgu-desktop.iind.intel.com ([10.223.82.83]) by azsmga001.ch.intel.com with ESMTP; 29 May 2014 02:39:31 -0700 From: sourab.gupta@intel.com To: intel-gfx@lists.freedesktop.org Date: Thu, 29 May 2014 15:10:15 +0530 Message-Id: <1401356415-13406-4-git-send-email-sourab.gupta@intel.com> X-Mailer: git-send-email 1.8.5.1 In-Reply-To: <1401356415-13406-1-git-send-email-sourab.gupta@intel.com> References: <20140528095653.GH18409@nuc-i3427.alporthouse.com> <1401356415-13406-1-git-send-email-sourab.gupta@intel.com> Cc: Deepak S , Akash Goel , Sourab Gupta Subject: [Intel-gfx] [PATCH 3/3] drm/i915: Make module param for MMIO flip selection as tristate X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.8 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Sourab Gupta This patch enhances the module parameter, 'use_mmio_flip' which enables MMIO flips, to make it tristate. The values being- 0: Force CS flip 1: Force MMIO flip (Gen5+) >1: Driver discretion is applied while selecting CS vs MMIO flip. For Valleyview, this driver selection happens based on the idleness of Blitter and Video engines. The Blitter and Video engines are in the same power well. So, if both are idle, we can use MMIO flips, Otherwise, we can use the BCS flips. This usecase can be modified and/or enhanced to cover more platforms. Signed-off-by: Sourab Gupta --- drivers/gpu/drm/i915/i915_params.c | 4 +++- drivers/gpu/drm/i915/intel_display.c | 42 ++++++++++++++++++++++++++++++------ 2 files changed, 38 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_params.c b/drivers/gpu/drm/i915/i915_params.c index e0d44df..9becd1e 100644 --- a/drivers/gpu/drm/i915/i915_params.c +++ b/drivers/gpu/drm/i915/i915_params.c @@ -159,4 +159,6 @@ MODULE_PARM_DESC(enable_cmd_parser, "Enable command parsing (1=enabled [default], 0=disabled)"); module_param_named(use_mmio_flip, i915.use_mmio_flip, bool, 0600); -MODULE_PARM_DESC(use_mmio_flip, "use MMIO flips (default: false)"); +MODULE_PARM_DESC(use_mmio_flip, "use MMIO page flips" + "(0 force CS, 1:force mmio, >1: driver selection)" + "(default: 0)"); diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 9dda965..a3d38d2 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -9185,22 +9185,50 @@ static int intel_gen7_queue_flip(struct drm_device *dev, static bool intel_use_mmio_flip(struct drm_device *dev) { - /* If module parameter is disabled, use CS flips. - * Otherwise, use MMIO flips starting from Gen5. + struct drm_i915_private *dev_priv = dev->dev_private; + bool use_mmio_flip = false; + + /* If module parameter is 0, force CS flip. + * If module parameter is 1, force MMIO flip starting from Gen5. * This is not being used for older platforms, because * non-availability of flip done interrupt forces us to use * CS flips. Older platforms derive flip done using some clever * tricks involving the flip_pending status bits and vblank irqs. * So using MMIO flips there would disrupt this mechanism. + * If module parameter is > 1, driver discretion is applied for + * selection of CS vs MMIO flip. */ if (i915.use_mmio_flip == 0) - return false; + use_mmio_flip = false; - if (INTEL_INFO(dev)->gen >= 5) - return true; - else - return false; + if (i915.use_mmio_flip == 1) { + if (INTEL_INFO(dev)->gen >= 5) + use_mmio_flip = true; + else + use_mmio_flip = false; + } + + if (i915.use_mmio_flip > 1) { + /* For Valleyview, Blitter and Video engines are in the same + * power well. So, if both are idle, we can use MMIO flips, + * Otherwise, we can use the BCS flips. + * We use the parameter 'request_list' to determine the idleness + * of the engine. + */ + if (IS_VALLEYVIEW(dev)) { + struct intel_engine_cs *bcs_ring = &dev_priv->ring[BCS]; + struct intel_engine_cs *vcs_ring = &dev_priv->ring[VCS]; + + if (list_empty(&bcs_ring->request_list) && + list_empty(&vcs_ring->request_list)) + use_mmio_flip = true; + else + use_mmio_flip = false; + } else + use_mmio_flip = false; + } + return use_mmio_flip; } static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)