diff mbox

drm/i915: Fix VLV CRC reading.

Message ID 1402003697-1671-1-git-send-email-rodrigo.vivi@intel.com (mailing list archive)
State New, archived
Headers show

Commit Message

Rodrigo Vivi June 5, 2014, 9:28 p.m. UTC 
Adding missing Display mmio reg offset.

Credits-to: Laws, Philip <philip.laws@intel.com>
Cc: He, Shuang <shuang.he@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Comments

Ville Syrjälä June 9, 2014, 11:42 a.m. UTC | #1 
On Thu, Jun 05, 2014 at 02:28:17PM -0700, Rodrigo Vivi wrote:
> Adding missing Display mmio reg offset.
> 
> Credits-to: Laws, Philip <philip.laws@intel.com>
> Cc: He, Shuang <shuang.he@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

> ---
>  drivers/gpu/drm/i915/i915_reg.h | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 286f05c..05e2541 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2627,7 +2627,7 @@ enum punit_power_well {
>  
>  #define PORT_DFT_I9XX				0x61150
>  #define   DC_BALANCE_RESET			(1 << 25)
> -#define PORT_DFT2_G4X				0x61154
> +#define PORT_DFT2_G4X		(dev_priv->info.display_mmio_offset + 0x61154)
>  #define   DC_BALANCE_RESET_VLV			(1 << 31)
>  #define   PIPE_SCRAMBLE_RESET_MASK		(0x3 << 0)
>  #define   PIPE_B_SCRAMBLE_RESET			(1 << 1)
> -- 
> 1.9.3
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Daniel Vetter June 10, 2014, 7:05 a.m. UTC | #2 
On Thu, Jun 05, 2014 at 02:28:17PM -0700, Rodrigo Vivi wrote:
> Adding missing Display mmio reg offset.
> 
> Credits-to: Laws, Philip <philip.laws@intel.com>
> Cc: He, Shuang <shuang.he@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

Is there no bugzilla that pipe crc tests on DP/eDP ports aren't working on
byt? Can you please chase this down with QA?

Patch is queued for -next.

Thanks, Daniel

> ---
>  drivers/gpu/drm/i915/i915_reg.h | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 286f05c..05e2541 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2627,7 +2627,7 @@ enum punit_power_well {
>  
>  #define PORT_DFT_I9XX				0x61150
>  #define   DC_BALANCE_RESET			(1 << 25)
> -#define PORT_DFT2_G4X				0x61154
> +#define PORT_DFT2_G4X		(dev_priv->info.display_mmio_offset + 0x61154)
>  #define   DC_BALANCE_RESET_VLV			(1 << 31)
>  #define   PIPE_SCRAMBLE_RESET_MASK		(0x3 << 0)
>  #define   PIPE_B_SCRAMBLE_RESET			(1 << 1)
> -- 
> 1.9.3
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
diff mbox

Patch

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 286f05c..05e2541 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2627,7 +2627,7 @@  enum punit_power_well {
 
 #define PORT_DFT_I9XX				0x61150
 #define   DC_BALANCE_RESET			(1 << 25)
-#define PORT_DFT2_G4X				0x61154
+#define PORT_DFT2_G4X		(dev_priv->info.display_mmio_offset + 0x61154)
 #define   DC_BALANCE_RESET_VLV			(1 << 31)
 #define   PIPE_SCRAMBLE_RESET_MASK		(0x3 << 0)
 #define   PIPE_B_SCRAMBLE_RESET			(1 << 1)