From patchwork Thu Jun 26 17:24:35 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Harrison X-Patchwork-Id: 4429331 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 75C96BEEAA for ; Thu, 26 Jun 2014 17:26:23 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 6A21A2038F for ; Thu, 26 Jun 2014 17:26:21 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 2E12520351 for ; Thu, 26 Jun 2014 17:26:17 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 6DA646E2EE; Thu, 26 Jun 2014 10:26:15 -0700 (PDT) X-Original-To: Intel-GFX@lists.freedesktop.org Delivered-To: Intel-GFX@lists.freedesktop.org Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTP id 76DC66E23B for ; Thu, 26 Jun 2014 10:26:08 -0700 (PDT) Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga101.fm.intel.com with ESMTP; 26 Jun 2014 10:26:08 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.01,554,1400050800"; d="scan'208";a="561435046" Received: from johnharr-linux.iwi.intel.com ([172.28.253.52]) by fmsmga002.fm.intel.com with ESMTP; 26 Jun 2014 10:25:56 -0700 From: John.C.Harrison@Intel.com To: Intel-GFX@lists.freedesktop.org Date: Thu, 26 Jun 2014 18:24:35 +0100 Message-Id: <1403803475-16337-45-git-send-email-John.C.Harrison@Intel.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1403803475-16337-1-git-send-email-John.C.Harrison@Intel.com> References: <1403803475-16337-1-git-send-email-John.C.Harrison@Intel.com> Organization: Intel Corporation (UK) Ltd. - Co. Reg. #1134945 - Pipers Way, Swindon SN3 1RJ Subject: [Intel-gfx] [RFC 44/44] drm/i915: Fake batch support for page flips X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: John Harrison Any commands written to the ring without the scheduler's knowledge can get lost during a pre-emption event. This checkin updates the page flip code to send the ring commands via the scheduler's 'fake batch' interface. Thus the page flip is kept safe from being clobbered. --- drivers/gpu/drm/i915/intel_display.c | 84 ++++++++++++++++------------------ 1 file changed, 40 insertions(+), 44 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index fa1ffbb..8bbc5d3 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -9099,8 +9099,8 @@ static int intel_gen7_queue_flip(struct drm_device *dev, uint32_t flags) { struct intel_crtc *intel_crtc = to_intel_crtc(crtc); - uint32_t plane_bit = 0; - int len, ret; + uint32_t plane_bit = 0, sched_flags; + int ret; switch (intel_crtc->plane) { case PLANE_A: @@ -9117,18 +9117,6 @@ static int intel_gen7_queue_flip(struct drm_device *dev, return -ENODEV; } - len = 4; - if (ring->id == RCS) { - len += 6; - /* - * On Gen 8, SRM is now taking an extra dword to accommodate - * 48bits addresses, and we need a NOOP for the batch size to - * stay even. - */ - if (IS_GEN8(dev)) - len += 2; - } - /* * BSpec MI_DISPLAY_FLIP for IVB: * "The full packet must be contained within the same cache line." @@ -9139,13 +9127,7 @@ static int intel_gen7_queue_flip(struct drm_device *dev, * then do the cacheline alignment, and finally emit the * MI_DISPLAY_FLIP. */ - ret = intel_ring_cacheline_align(ring); - if (ret) - return ret; - - ret = intel_ring_begin(ring, len); - if (ret) - return ret; + sched_flags = i915_ebp_sf_cacheline_align; /* Unmask the flip-done completion message. Note that the bspec says that * we should do this for both the BCS and RCS, and that we must not unmask @@ -9157,32 +9139,46 @@ static int intel_gen7_queue_flip(struct drm_device *dev, * to zero does lead to lockups within MI_DISPLAY_FLIP. */ if (ring->id == RCS) { - intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); - intel_ring_emit(ring, DERRMR); - intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE | - DERRMR_PIPEB_PRI_FLIP_DONE | - DERRMR_PIPEC_PRI_FLIP_DONE)); - if (IS_GEN8(dev)) - intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) | - MI_SRM_LRM_GLOBAL_GTT); - else - intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) | - MI_SRM_LRM_GLOBAL_GTT); - intel_ring_emit(ring, DERRMR); - intel_ring_emit(ring, ring->scratch.gtt_offset + 256); - if (IS_GEN8(dev)) { - intel_ring_emit(ring, 0); - intel_ring_emit(ring, MI_NOOP); - } - } + uint32_t cmds[] = { + MI_LOAD_REGISTER_IMM(1), + DERRMR, + ~(DERRMR_PIPEA_PRI_FLIP_DONE | + DERRMR_PIPEB_PRI_FLIP_DONE | + DERRMR_PIPEC_PRI_FLIP_DONE), + IS_GEN8(dev) ? (MI_STORE_REGISTER_MEM_GEN8(1) | + MI_SRM_LRM_GLOBAL_GTT) : + (MI_STORE_REGISTER_MEM(1) | + MI_SRM_LRM_GLOBAL_GTT), + DERRMR, + ring->scratch.gtt_offset + 256, +// if (IS_GEN8(dev)) { + 0, + MI_NOOP, +// } + MI_DISPLAY_FLIP_I915 | plane_bit, + fb->pitches[0] | obj->tiling_mode, + intel_crtc->unpin_work->gtt_offset, + MI_NOOP + }; + uint32_t len = sizeof(cmds) / sizeof(*cmds); + + ret = i915_scheduler_queue_nonbatch(ring, cmds, len, &obj, 1, sched_flags); + } else { + uint32_t cmds[] = { + MI_DISPLAY_FLIP_I915 | plane_bit, + fb->pitches[0] | obj->tiling_mode, + intel_crtc->unpin_work->gtt_offset, + MI_NOOP + }; + uint32_t len = sizeof(cmds) / sizeof(*cmds); - intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit); - intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode)); - intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); - intel_ring_emit(ring, (MI_NOOP)); + ret = i915_scheduler_queue_nonbatch(ring, cmds, len, &obj, 1, sched_flags); + } + if (ret) + return ret; intel_mark_page_flip_active(intel_crtc); - i915_add_request_wo_flush(ring); + return 0; }