From patchwork Fri Jul 4 14:27:39 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paulo Zanoni X-Patchwork-Id: 4481571 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 35BDE9F26C for ; Fri, 4 Jul 2014 14:28:18 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 48F42203E3 for ; Fri, 4 Jul 2014 14:28:17 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 7E8A8203C4 for ; Fri, 4 Jul 2014 14:28:15 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 10BF66E7F9; Fri, 4 Jul 2014 07:28:15 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-yk0-f170.google.com (mail-yk0-f170.google.com [209.85.160.170]) by gabe.freedesktop.org (Postfix) with ESMTP id E45B76E7F8 for ; Fri, 4 Jul 2014 07:28:12 -0700 (PDT) Received: by mail-yk0-f170.google.com with SMTP id q9so697586ykb.29 for ; Fri, 04 Jul 2014 07:28:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=PD6wknP1+Pnwx680E7wFF1Ca8l8oI2Ivwr6L6xlst4s=; b=RC2JoA0LamPWBxTw7C5f7uocOucmeY80zqbCi35Q3kHKbq6zXkiyQ2DRauvxcbMM36 L3lNKloA5mi/Kx7FKU5puooga3a42D6DHZDdunhYP2iJ9PrrOdr7g4ldwMogegosz3N8 fzeQG9dBnW3nBjyJWw/UMOdDiAC1lPNEPTn+zPRMAE+PQd124TkQOGzf7m4N8dykI3Ei RLxV++noquDIdkEQE4UQ9a5ga5h6KOBR883PR/HVM2Q/L7hWTlnEwPzRoe+JNZ7gK+TI yrkifMahS7X09NlLSx0TYrgKgifMLlDDf1TQ9tpcYyRkYOgkXC9gHHB/3XCjUyCniAJc 0QOQ== X-Received: by 10.236.201.226 with SMTP id b62mr17245865yho.56.1404484092492; Fri, 04 Jul 2014 07:28:12 -0700 (PDT) Received: from localhost.localdomain ([177.16.191.220]) by mx.google.com with ESMTPSA id l46sm46659039yhq.44.2014.07.04.07.28.11 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 04 Jul 2014 07:28:12 -0700 (PDT) From: Paulo Zanoni To: intel-gfx@lists.freedesktop.org Date: Fri, 4 Jul 2014 11:27:39 -0300 Message-Id: <1404484059-4236-2-git-send-email-przanoni@gmail.com> X-Mailer: git-send-email 2.0.0 In-Reply-To: <1404484059-4236-1-git-send-email-przanoni@gmail.com> References: <1403722924-26738-15-git-send-email-imre.deak@intel.com> <1404484059-4236-1-git-send-email-przanoni@gmail.com> Cc: Daniel Vetter , Paulo Zanoni Subject: [Intel-gfx] [PATCH 14/19] drm/i915: State readout support for WRPLLs X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.1 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_MED, T_DKIM_INVALID, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Daniel Vetter Still tacked onto the side, but slowly getting there. v2: Don't forget the debugfs file. v3 (from Paulo): Don't forget to check the power domains. Signed-off-by: Daniel Vetter Reviewed-by: Damien Lespiau Signed-off-by: Paulo Zanoni --- drivers/gpu/drm/i915/i915_debugfs.c | 1 + drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/drm/i915/i915_reg.h | 1 + drivers/gpu/drm/i915/intel_ddi.c | 19 +++++++++++++++++++ drivers/gpu/drm/i915/intel_display.c | 9 +++++++++ 5 files changed, 31 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index e79ddbf..7d72768 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -2409,6 +2409,7 @@ static int i915_shared_dplls_info(struct seq_file *m, void *unused) seq_printf(m, " dpll_md: 0x%08x\n", pll->hw_state.dpll_md); seq_printf(m, " fp0: 0x%08x\n", pll->hw_state.fp0); seq_printf(m, " fp1: 0x%08x\n", pll->hw_state.fp1); + seq_printf(m, " wrpll: 0x%08x\n", pll->hw_state.wrpll); } drm_modeset_unlock_all(dev); diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 2ec7cb6..c1fa561 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -197,6 +197,7 @@ struct intel_dpll_hw_state { uint32_t dpll_md; uint32_t fp0; uint32_t fp1; + uint32_t wrpll; }; struct intel_shared_dpll { diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 3d61a53..654417e 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -5900,6 +5900,7 @@ enum punit_power_well { /* WRPLL */ #define WRPLL_CTL1 0x46040 #define WRPLL_CTL2 0x46060 +#define WRPLL_CTL(pll) (pll == 0 ? WRPLL_CTL1 : WRPLL_CTL2) #define WRPLL_PLL_ENABLE (1<<31) #define WRPLL_PLL_SSC (1<<28) #define WRPLL_PLL_NON_SSC (2<<28) diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c index fae73d3..79cbb5e 100644 --- a/drivers/gpu/drm/i915/intel_ddi.c +++ b/drivers/gpu/drm/i915/intel_ddi.c @@ -790,6 +790,8 @@ bool intel_ddi_pll_select(struct intel_crtc *intel_crtc) intel_crtc->config.ddi_pll_sel = PORT_CLK_SEL_WRPLL2; intel_crtc->config.shared_dpll = DPLL_ID_WRPLL2; } + + intel_crtc->config.dpll_hw_state.wrpll = val; } return true; @@ -1315,6 +1317,21 @@ int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv) } } +static bool hsw_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv, + struct intel_shared_dpll *pll, + struct intel_dpll_hw_state *hw_state) +{ + uint32_t val; + + if (!intel_display_power_enabled(dev_priv, POWER_DOMAIN_PLLS)) + return false; + + val = I915_READ(WRPLL_CTL(pll->id)); + hw_state->wrpll = val; + + return val & WRPLL_PLL_ENABLE; +} + static char *hsw_ddi_pll_names[] = { "WRPLL 1", "WRPLL 2", @@ -1333,6 +1350,8 @@ void intel_ddi_pll_init(struct drm_device *dev) for (i = 0; i < 2; i++) { dev_priv->shared_dplls[i].id = i; dev_priv->shared_dplls[i].name = hsw_ddi_pll_names[i]; + dev_priv->shared_dplls[i].get_hw_state = + hsw_ddi_pll_get_hw_state; } /* The LCPLL register should be turned on by the BIOS. For now let's diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 1d919ae..594a49f 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -7587,6 +7587,7 @@ static void haswell_get_ddi_port_state(struct intel_crtc *crtc, { struct drm_device *dev = crtc->base.dev; struct drm_i915_private *dev_priv = dev->dev_private; + struct intel_shared_dpll *pll; enum port port; uint32_t tmp; @@ -7605,6 +7606,13 @@ static void haswell_get_ddi_port_state(struct intel_crtc *crtc, break; } + if (pipe_config->shared_dpll >= 0) { + pll = &dev_priv->shared_dplls[pipe_config->shared_dpll]; + + WARN_ON(!pll->get_hw_state(dev_priv, pll, + &pipe_config->dpll_hw_state)); + } + /* * Haswell has only FDI/PCH transcoder A. It is which is connected to * DDI E. So just check whether this pipe is wired to DDI E and whether @@ -10436,6 +10444,7 @@ intel_pipe_config_compare(struct drm_device *dev, PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md); PIPE_CONF_CHECK_X(dpll_hw_state.fp0); PIPE_CONF_CHECK_X(dpll_hw_state.fp1); + PIPE_CONF_CHECK_X(dpll_hw_state.wrpll); if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) PIPE_CONF_CHECK_I(pipe_bpp);