Message ID | 1404485433-4488-3-git-send-email-przanoni@gmail.com (mailing list archive) |
---|---|
State | New, archived |
Headers | show |
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> On Fri, Jul 4, 2014 at 7:50 AM, Paulo Zanoni <przanoni@gmail.com> wrote: > From: Paulo Zanoni <paulo.r.zanoni@intel.com> > > So don't write it, otherwise we will trigger unclaimed register > errors. > > Testcase: igt/pm_rpm/rte > Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> > --- > drivers/gpu/drm/i915/intel_display.c | 5 +++-- > 1 file changed, 3 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_display.c > b/drivers/gpu/drm/i915/intel_display.c > index c12a5da..14505a1 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -7345,8 +7345,9 @@ static void assert_can_disable_lcpll(struct > drm_i915_private *dev_priv) > WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n"); > WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE, > "CPU PWM1 enabled\n"); > - WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE, > - "CPU PWM2 enabled\n"); > + if (IS_HASWELL(dev)) > + WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE, > + "CPU PWM2 enabled\n"); > WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE, > "PCH PWM1 enabled\n"); > WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE, > -- > 2.0.0 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx >
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index c12a5da..14505a1 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -7345,8 +7345,9 @@ static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv) WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n"); WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE, "CPU PWM1 enabled\n"); - WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE, - "CPU PWM2 enabled\n"); + if (IS_HASWELL(dev)) + WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE, + "CPU PWM2 enabled\n"); WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE, "PCH PWM1 enabled\n"); WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,