diff mbox

drm/i915/bdw: 3D_CHICKEN3 has write mask bits

Message ID 1404733217-13185-1-git-send-email-michel.thierry@intel.com (mailing list archive)
State New, archived
Headers show

Commit Message

Michel Thierry July 7, 2014, 11:40 a.m. UTC 
From: Michel Thierry <michel.thierry@intel.com>

The workaround to limit SDE poly depth FIFO to 2 is not applied because
3D Chicken-3 mask bit is not set.

WaLimitSizeOfSDEPolyFifo is only for BDW-A and could be removed.

Signed-off-by: Michel Thierry <michel.thierry@intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Comments

Mika Kuoppala July 7, 2014, 1:06 p.m. UTC | #1 
michel.thierry@intel.com writes:

> From: Michel Thierry <michel.thierry@intel.com>
>
> The workaround to limit SDE poly depth FIFO to 2 is not applied because
> 3D Chicken-3 mask bit is not set.
>
> WaLimitSizeOfSDEPolyFifo is only for BDW-A and could be removed.
>
> Signed-off-by: Michel Thierry <michel.thierry@intel.com>
Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>

> ---
>  drivers/gpu/drm/i915/intel_pm.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 31ae2b4..ae68df6 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -5360,7 +5360,7 @@ static void gen8_init_clock_gating(struct drm_device *dev)
>  	I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_BWGTLB_DISABLE));
>  
>  	I915_WRITE(_3D_CHICKEN3,
> -		   _3D_CHICKEN_SDE_LIMIT_FIFO_POLY_DEPTH(2));
> +		   _MASKED_BIT_ENABLE(_3D_CHICKEN_SDE_LIMIT_FIFO_POLY_DEPTH(2)));
>  
>  	I915_WRITE(COMMON_SLICE_CHICKEN2,
>  		   _MASKED_BIT_ENABLE(GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE));
> -- 
> 1.9.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Daniel Vetter July 7, 2014, 4:31 p.m. UTC | #2 
On Mon, Jul 07, 2014 at 04:06:02PM +0300, Mika Kuoppala wrote:
> michel.thierry@intel.com writes:
> 
> > From: Michel Thierry <michel.thierry@intel.com>
> >
> > The workaround to limit SDE poly depth FIFO to 2 is not applied because
> > 3D Chicken-3 mask bit is not set.
> >
> > WaLimitSizeOfSDEPolyFifo is only for BDW-A and could be removed.
> >
> > Signed-off-by: Michel Thierry <michel.thierry@intel.com>
> Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>

Queued for -next, thanks for the patch.
-Daniel
diff mbox

Patch

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 31ae2b4..ae68df6 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -5360,7 +5360,7 @@  static void gen8_init_clock_gating(struct drm_device *dev)
 	I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_BWGTLB_DISABLE));
 
 	I915_WRITE(_3D_CHICKEN3,
-		   _3D_CHICKEN_SDE_LIMIT_FIFO_POLY_DEPTH(2));
+		   _MASKED_BIT_ENABLE(_3D_CHICKEN_SDE_LIMIT_FIFO_POLY_DEPTH(2)));
 
 	I915_WRITE(COMMON_SLICE_CHICKEN2,
 		   _MASKED_BIT_ENABLE(GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE));