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[6/8] drm/i915: Add WaIncreaseTagClockTimer:bdw

Message ID 1405427135-11377-7-git-send-email-michel.thierry@intel.com (mailing list archive)
State New, archived
Headers show

Commit Message

Michel Thierry July 15, 2014, 12:25 p.m. UTC 
Workaround requires programing L3 tag clock timing register.

Signed-off-by: Michel Thierry <michel.thierry@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 4 ++++
 drivers/gpu/drm/i915/intel_pm.c | 9 +++++++++
 2 files changed, 13 insertions(+)
diff mbox

Patch

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 55ea3bf..ff1acbe 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4709,6 +4709,10 @@  enum punit_power_well {
 #define GEN8_L3SQCREG1				0xb100
 #define  GEN8_L3SQCREG1_DEFAULT_VALUE	0x784000
 
+#define GEN8_L3CNTLREG1				0xb10c
+#define  GEN8_TAG_CLK_OFFTIME			(1<<23)
+#define  GEN8_TAG_CLK_OFFTIME_MASK		(~((1<<23) | (1<<22) | (1<<21) | (1<<20)))
+
 #define GEN8_L3SQCREG4				0xb118
 #define  GEN8_PIPELINE_FLUSH_COHERENT_LINES	(1<<21)
 
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index b60fbd2..64e3245 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -5496,6 +5496,15 @@  static void gen8_init_clock_gating(struct drm_device *dev)
 	/* WaFlushCoherentL3CacheLinesAtContextSwitch:bdw */
 	I915_WRITE(GEN8_L3SQCREG4, I915_READ(GEN8_L3SQCREG4) |
 			GEN8_PIPELINE_FLUSH_COHERENT_LINES);
+
+	/*
+	 * WaIncreaseTagClockTimer:bdw
+	 * This register is not masked and the default value is not all zero.
+	 * Use the mask with and to clear out bits 23:20.
+	 */
+	I915_WRITE(GEN8_L3CNTLREG1, (I915_READ(GEN8_L3CNTLREG1) &
+			GEN8_TAG_CLK_OFFTIME_MASK) |
+			GEN8_TAG_CLK_OFFTIME);
 }
 
 static void haswell_init_clock_gating(struct drm_device *dev)