From patchwork Wed Jul 23 18:04:58 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Sharma, Shashank" X-Patchwork-Id: 4612411 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id CE474C0514 for ; Wed, 23 Jul 2014 18:01:58 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id F36B7201C8 for ; Wed, 23 Jul 2014 18:01:54 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 1BAD520172 for ; Wed, 23 Jul 2014 18:01:51 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id BCA146E687; Wed, 23 Jul 2014 11:01:50 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTP id 2CB0E6E373 for ; Wed, 23 Jul 2014 11:01:49 -0700 (PDT) Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga102.fm.intel.com with ESMTP; 23 Jul 2014 11:01:48 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.01,718,1400050800"; d="scan'208";a="574341166" Received: from shashanks-desktop.iind.intel.com ([10.223.26.11]) by fmsmga002.fm.intel.com with ESMTP; 23 Jul 2014 11:00:38 -0700 From: shashank.sharma@intel.com To: intel-gfx@lists.freedesktop.org, ville.syrjala@linux.intel.com, damien.lespiau@intel.com, daniel.vetter@intel.com, shobhit.kumar@intel.com, satheeshakrishna.m@intel.com Date: Wed, 23 Jul 2014 23:34:58 +0530 Message-Id: <1406138705-17334-5-git-send-email-shashank.sharma@intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1406138705-17334-1-git-send-email-shashank.sharma@intel.com> References: <1406138705-17334-1-git-send-email-shashank.sharma@intel.com> Cc: =indranil.mukherjee@intel.com Subject: [Intel-gfx] [PATCH 04/11] drm/i915: Add color manager CSC correction X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Shashank Sharma This patch adds support for pipe CSC correction color property for intel color manager framework. It adds two functions: 1. intel_clrmgr_set_csc: This is a wrapper function which checks the platform type, and calls the valleyview specific set_csc function. As different platforms have different methods of setting CSC, this function is required.The support for other platfroms can be plugged-in here in the wrapper function. Adding this function as .set_property CSC color property. 2. vlv_set_csc: core function to program CSC coefficients as per vlv specs, and then enable CSC. Signed-off-by: Shashank Sharma --- drivers/gpu/drm/i915/i915_reg.h | 11 +++++ drivers/gpu/drm/i915/intel_clrmgr.c | 82 +++++++++++++++++++++++++++++++++++++ drivers/gpu/drm/i915/intel_clrmgr.h | 16 ++++++++ 3 files changed, 109 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index fe5c276..3199f96 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -6084,6 +6084,17 @@ enum punit_power_well { #define PIPE_CSC_POSTOFF_ME(pipe) _PIPE(pipe, _PIPE_A_CSC_POSTOFF_ME, _PIPE_B_CSC_POSTOFF_ME) #define PIPE_CSC_POSTOFF_LO(pipe) _PIPE(pipe, _PIPE_A_CSC_POSTOFF_LO, _PIPE_B_CSC_POSTOFF_LO) +/* VLV color correction registers */ +/* CSC */ +#define PIPECONF_CSC_ENABLE (1 << 15) +#define _PIPEACSC (dev_priv->info.display_mmio_offset + \ + 0x600b0) +#define _PIPEBCSC (dev_priv->info.display_mmio_offset + \ + 0x610b0) +#define PIPECSC(pipe) (_PIPEACSC + (pipe * CSC_OFFSET)) +#define CSC_OFFSET (_PIPEBCSC - _PIPEACSC) +#define PIPECSC(pipe) (_PIPEACSC + (pipe * CSC_OFFSET)) + /* VLV MIPI registers */ #define _MIPIA_PORT_CTRL (VLV_DISPLAY_BASE + 0x61190) diff --git a/drivers/gpu/drm/i915/intel_clrmgr.c b/drivers/gpu/drm/i915/intel_clrmgr.c index 0aa3734..601076b 100644 --- a/drivers/gpu/drm/i915/intel_clrmgr.c +++ b/drivers/gpu/drm/i915/intel_clrmgr.c @@ -44,6 +44,7 @@ struct clrmgr_property gen6_pipe_color_corrections[] = { .type = DRM_MODE_PROP_BLOB, .len = VLV_CSC_MATRIX_MAX_VALS, .name = "csc-correction", + .set_property = intel_clrmgr_set_csc, }, { .tweak_id = gamma, @@ -87,6 +88,87 @@ struct clrmgr_property gen6_plane_color_corrections[] = { } }; +/* +* vlv_set_csc +* Valleyview specific csc correction method. +* Programs the 6 csc registers with 3x3 correction matrix +* values. +* inputs: +* - intel_crtc* +* - color manager registered property for csc correction +* - data: pointer to correction values to be applied +*/ +/* Enable color space conversion on PIPE */ +bool vlv_set_csc(struct intel_crtc *intel_crtc, + struct clrmgr_regd_prop *csc, u64 *data) +{ + u32 count = 0; + u32 pipeconf, csc_reg, data_size; + struct drm_device *dev = intel_crtc->base.dev; + struct drm_i915_private *dev_priv = dev->dev_private; + struct drm_property *property; + u32 c0, c1, c2; + + property = csc->property; + data_size = property->num_values; + + /* Validate input */ + if (data_size != VLV_CSC_MATRIX_MAX_VALS) { + DRM_ERROR("Unexpected value count for GAMMA LUT\n"); + return false; + } + + DRM_DEBUG_DRIVER("Setting CSC on pipe = %d\n", intel_crtc->pipe); + csc_reg = PIPECSC(intel_crtc->pipe); + + /* Read CSC matrix, one row at a time */ + while (count < VLV_CSC_MATRIX_MAX_VALS) { + c0 = data[count] & VLV_CSC_VALUE_MASK; + property->values[count++] = c0; + c1 = data[count] & VLV_CSC_VALUE_MASK; + property->values[count++] = c1; + c2 = data[count] & VLV_CSC_VALUE_MASK; + property->values[count++] = c2; + + /* C0 is LSB 12bits, C1 is MSB 16-27 */ + I915_WRITE(csc_reg, (c1 << VLV_CSC_COEFF_SHIFT) | c0); + csc_reg += 4; + + /* C2 is LSB 12 bits */ + I915_WRITE(csc_reg, c2); + csc_reg += 4; + } + + /* Enable csc correction */ + pipeconf = I915_READ(PIPECONF(intel_crtc->pipe)) | PIPECONF_CSC_ENABLE; + I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf); + POSTING_READ(PIPECONF(intel_crtc->pipe)); + + DRM_DEBUG_DRIVER("CSC successfully set on pipe = %d\n", + intel_crtc->pipe); + return true; +} + +bool intel_clrmgr_set_csc(void *crtc, + struct clrmgr_regd_prop *csc, u64 *data) +{ + struct intel_crtc *intel_crtc = crtc; + struct drm_device *dev = intel_crtc->base.dev; + + /* Validate input */ + if (!data || !csc || !csc->property) { + DRM_ERROR("Invalid input to set csc\n"); + return false; + } + + /* VLV has legacy palette gamma correction */ + if (IS_VALLEYVIEW(dev)) + return vlv_set_csc(intel_crtc, csc, data); + + /* Todo: Support other gen devices */ + DRM_ERROR("Color correction is supported only on VLV for now\n"); + return false; +} struct drm_property *intel_clrmgr_register(struct drm_device *dev, struct drm_mode_object *obj, struct clrmgr_property *cp) diff --git a/drivers/gpu/drm/i915/intel_clrmgr.h b/drivers/gpu/drm/i915/intel_clrmgr.h index 28fea24..e1279f6 100644 --- a/drivers/gpu/drm/i915/intel_clrmgr.h +++ b/drivers/gpu/drm/i915/intel_clrmgr.h @@ -43,6 +43,9 @@ /* CSC / Wide gamut */ #define VLV_CSC_MATRIX_MAX_VALS 9 +#define VLV_CSC_VALUE_MASK 0xFFF +#define VLV_CSC_COEFF_SHIFT 16 + /* VLV specific gamma correction defines */ #define VLV_10BIT_GAMMA_MAX_INDEX 128 @@ -116,6 +119,19 @@ struct clrmgr_reg_request { }; /* +* intel_clrmgr_set_csc +* CSC correction method is different across various +* gen devices. This wrapper function calls the respective +* platform specific function to set CSC +* inputs: +* - crtc: void *, can be typecaseted to intel_crtc* +* - csc: registered color property for csc correction +* - data: pointer to correction values to be applied +*/ +bool intel_clrmgr_set_csc(void *crtc, + struct clrmgr_regd_prop *csc, u64 *data); + +/* * intel_clrmgr_register_pipe_property * register set of properties with a CRTC * input: