From patchwork Thu Jul 31 12:36:44 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: sagar.a.kamble@intel.com X-Patchwork-Id: 4655981 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id BF5059F32F for ; Thu, 31 Jul 2014 12:35:55 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id AD1E320138 for ; Thu, 31 Jul 2014 12:35:54 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 9477620121 for ; Thu, 31 Jul 2014 12:35:53 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 822136E28B; Thu, 31 Jul 2014 05:35:52 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTP id 4C3E36E28B for ; Thu, 31 Jul 2014 05:35:51 -0700 (PDT) Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga102.fm.intel.com with ESMTP; 31 Jul 2014 05:35:51 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.01,772,1400050800"; d="scan'208";a="578188711" Received: from sagar-desktop.iind.intel.com ([10.223.82.56]) by fmsmga002.fm.intel.com with ESMTP; 31 Jul 2014 05:35:46 -0700 From: sagar.a.kamble@intel.com To: intel-gfx@lists.freedesktop.org Date: Thu, 31 Jul 2014 18:06:44 +0530 Message-Id: <1406810204-5482-1-git-send-email-sagar.a.kamble@intel.com> X-Mailer: git-send-email 1.8.5 In-Reply-To: <20140728185140.GI4747@phenom.ffwll.local> References: <20140728185140.GI4747@phenom.ffwll.local> Cc: Sagar Kamble Subject: [Intel-gfx] [RFC 1/1] FOR_UPSTREAM [VPG]: drm/i915: Adding Gfx Clock, Wake and Gunit save/restore logic in PM suspend/resume paths. X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Sagar Kamble Sequence to get gfx clocks on/off, allow/disallow wake and save/restore of gunit registers need to be followed in PM suspend and resume path similar to runtime suspend and resume. v2: 1. Keeping GT access, wake, gunit save/restore related helpers static. 2. Moved GT access check, Wake Control, Gunit state save to end of i915_drm_freeze. 3. Reusing the sequence in runtime_suspend/resume path at macro level. Issue: GMIN-2507 Change-Id: I15cfdeeec9c976d9839bb281f809664f4a0c78a2 Signed-off-by: Sagar Kamble --- drivers/gpu/drm/i915/i915_drv.c | 39 +++++++++++++++++++++++++++++++++------ drivers/gpu/drm/i915/i915_drv.h | 1 + 2 files changed, 34 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index 6c4b25c..385dc74 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -490,11 +490,16 @@ bool i915_semaphore_is_enabled(struct drm_device *dev) return true; } +static int vlv_runtime_suspend(struct drm_i915_private *dev_priv); +static int vlv_runtime_resume(struct drm_i915_private *dev_priv, + bool resume_from_s0ix); + static int i915_drm_freeze(struct drm_device *dev) { struct drm_i915_private *dev_priv = dev->dev_private; struct drm_crtc *crtc; pci_power_t opregion_target_state; + int ret = 0; /* ignore lid events during suspend */ mutex_lock(&dev_priv->modeset_restore_lock); @@ -562,7 +567,12 @@ static int i915_drm_freeze(struct drm_device *dev) intel_display_set_init_power(dev_priv, false); - return 0; + /* Save Gunit State and clear wake - Need to make sure + * changes in vlv_runtime_suspend path don't impact this path */ + if (IS_VALLEYVIEW(dev)) + ret = vlv_runtime_suspend(dev_priv); + + return ret; } int i915_suspend(struct drm_device *dev, pm_message_t state) @@ -610,6 +620,12 @@ void intel_console_resume(struct work_struct *work) static int i915_drm_thaw_early(struct drm_device *dev) { struct drm_i915_private *dev_priv = dev->dev_private; + int ret = 0; + + /* Restore Gunit State and allow wake - Need to make sure + * changes in vlv_runtime_resume path don't impact this path */ + if (IS_VALLEYVIEW(dev)) + ret = vlv_runtime_resume(dev_priv, true); if (IS_HASWELL(dev) || IS_BROADWELL(dev)) hsw_disable_pc8(dev_priv); @@ -618,7 +634,7 @@ static int i915_drm_thaw_early(struct drm_device *dev) intel_uncore_sanitize(dev); intel_power_domains_init_hw(dev_priv); - return 0; + return ret; } static int __i915_drm_thaw(struct drm_device *dev, bool restore_gtt_mappings) @@ -1098,6 +1114,7 @@ static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv) s->gu_ctl0 = I915_READ(VLV_GU_CTL0); s->gu_ctl1 = I915_READ(VLV_GU_CTL1); s->clock_gate_dis2 = I915_READ(VLV_GUNIT_CLOCK_GATE2); + s->dpio_cfg_data = I915_READ(DPIO_CTL); /* * Not saving any of: @@ -1192,6 +1209,7 @@ static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv) I915_WRITE(VLV_GU_CTL0, s->gu_ctl0); I915_WRITE(VLV_GU_CTL1, s->gu_ctl1); I915_WRITE(VLV_GUNIT_CLOCK_GATE2, s->clock_gate_dis2); + I915_WRITE(DPIO_CTL, s->dpio_cfg_data); } int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool force_on) @@ -1291,6 +1309,8 @@ static void vlv_check_no_gt_access(struct drm_i915_private *dev_priv) I915_WRITE(VLV_GTLC_PW_STATUS, VLV_GTLC_ALLOWWAKEERR); } +/* This function is used in system suspend path as well to utilize + * Gfx clock, Wake control, Gunit state save related functionaility */ static int vlv_runtime_suspend(struct drm_i915_private *dev_priv) { u32 mask; @@ -1331,7 +1351,12 @@ err1: return err; } -static int vlv_runtime_resume(struct drm_i915_private *dev_priv) +/* This function is used in system resume path as well to utilize + * Gfx clock, Wake control, Gunit state restore related functionaility. + * GEM and other initialization will differ which will be controlled by + * resume_from_s0ix variable */ +static int vlv_runtime_resume(struct drm_i915_private *dev_priv, + bool resume_from_s0ix) { struct drm_device *dev = dev_priv->dev; int err; @@ -1356,8 +1381,10 @@ static int vlv_runtime_resume(struct drm_i915_private *dev_priv) vlv_check_no_gt_access(dev_priv); - intel_init_clock_gating(dev); - i915_gem_restore_fences(dev); + if (!resume_from_s0ix) { + intel_init_clock_gating(dev); + i915_gem_restore_fences(dev); + } return ret; } @@ -1462,7 +1489,7 @@ static int intel_runtime_resume(struct device *device) } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { ret = hsw_runtime_resume(dev_priv); } else if (IS_VALLEYVIEW(dev)) { - ret = vlv_runtime_resume(dev_priv); + ret = vlv_runtime_resume(dev_priv, false); } else { WARN_ON(1); ret = -ENODEV; diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index d604f4f..3a836c9 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -910,6 +910,7 @@ struct vlv_s0ix_state { u32 gu_ctl0; u32 gu_ctl1; u32 clock_gate_dis2; + u32 dpio_cfg_data; }; struct intel_rps_ei {