From patchwork Mon Aug 4 18:15:15 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rodrigo Vivi X-Patchwork-Id: 4674201 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 2DD68C033A for ; Tue, 5 Aug 2014 01:14:26 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 29CD320173 for ; Tue, 5 Aug 2014 01:14:25 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 06D0320166 for ; Tue, 5 Aug 2014 01:14:24 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id A1A516E487; Mon, 4 Aug 2014 18:14:20 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTP id EE8DD89E5A for ; Mon, 4 Aug 2014 18:14:18 -0700 (PDT) Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga101.jf.intel.com with ESMTP; 04 Aug 2014 18:14:18 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.01,801,1400050800"; d="scan'208";a="583413773" Received: from di-604.jf.intel.com (HELO rdvivi-hillsboro.jf.intel.com) ([10.7.196.77]) by orsmga002.jf.intel.com with ESMTP; 04 Aug 2014 18:14:17 -0700 From: Rodrigo Vivi To: intel-gfx@lists.freedesktop.org Date: Mon, 4 Aug 2014 11:15:15 -0700 Message-Id: <1407176119-5294-3-git-send-email-rodrigo.vivi@intel.com> X-Mailer: git-send-email 1.9.3 In-Reply-To: <1407176119-5294-1-git-send-email-rodrigo.vivi@intel.com> References: <1407176119-5294-1-git-send-email-rodrigo.vivi@intel.com> Cc: Ben Widawsky , Rodrigo Vivi , Ben Widawsky Subject: [Intel-gfx] [PATCH 3/7] drm/i915/bdw: MI_FLUSH_DW a qword instead of dword X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-3.3 required=5.0 tests=BAYES_00, DATE_IN_PAST_06_12, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Ben Widawsky The actual post sync op is "Write Immediate Data QWord." It is therefore arguable that we should have always done a qword write. The actual impetus for this patch is our decoder complains when we write a dword and I was trying to eliminate the spurious errors. With this patch, I've noticed a really strange reproducible error turns into a different strange reproducible error - so it does indeed have some effect of some sort. This was also recommended to me by someone that is familiar with the Windows driver. It's based on top of the semaphore series, so it won't be easily applied, I'd guess. Signed-off-by: Ben Widawsky Signed-off-by: Rodrigo Vivi --- drivers/gpu/drm/i915/intel_ringbuffer.c | 95 +++++++++++++++++++++++++-------- 1 file changed, 74 insertions(+), 21 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index 2908896..9a562b5 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -727,7 +727,7 @@ static int gen8_rcs_signal(struct intel_engine_cs *signaller, static int gen8_xcs_signal(struct intel_engine_cs *signaller, unsigned int num_dwords) { -#define MBOX_UPDATE_DWORDS 6 +#define MBOX_UPDATE_DWORDS 8 struct drm_device *dev = signaller->dev; struct drm_i915_private *dev_priv = dev->dev_private; struct intel_engine_cs *waiter; @@ -746,15 +746,18 @@ static int gen8_xcs_signal(struct intel_engine_cs *signaller, if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID) continue; - intel_ring_emit(signaller, (MI_FLUSH_DW + 1) | + intel_ring_emit(signaller, (MI_FLUSH_DW + 2) | MI_FLUSH_DW_OP_STOREDW); intel_ring_emit(signaller, lower_32_bits(gtt_offset) | MI_FLUSH_DW_USE_GTT); intel_ring_emit(signaller, upper_32_bits(gtt_offset)); intel_ring_emit(signaller, signaller->outstanding_lazy_seqno); + intel_ring_emit(signaller, 0); /* upper dword */ + intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL | MI_SEMAPHORE_TARGET(waiter->id)); intel_ring_emit(signaller, 0); + intel_ring_emit(signaller, MI_NOOP); } return 0; @@ -1939,8 +1942,6 @@ static int gen6_bsd_ring_flush(struct intel_engine_cs *ring, return ret; cmd = MI_FLUSH_DW; - if (INTEL_INFO(ring->dev)->gen >= 8) - cmd += 1; /* * Bspec vol 1c.5 - video engine command streamer: * "If ENABLED, all TLBs will be invalidated once the flush @@ -1952,13 +1953,38 @@ static int gen6_bsd_ring_flush(struct intel_engine_cs *ring, MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW; intel_ring_emit(ring, cmd); intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT); - if (INTEL_INFO(ring->dev)->gen >= 8) { - intel_ring_emit(ring, 0); /* upper addr */ - intel_ring_emit(ring, 0); /* value */ - } else { - intel_ring_emit(ring, 0); - intel_ring_emit(ring, MI_NOOP); - } + intel_ring_emit(ring, 0); + intel_ring_emit(ring, MI_NOOP); + intel_ring_advance(ring); + return 0; +} + +static int gen8_bsd_ring_flush(struct intel_engine_cs *ring, + u32 invalidate, u32 flush) +{ + uint32_t cmd; + int ret; + + ret = intel_ring_begin(ring, 6); + if (ret) + return ret; + + cmd = MI_FLUSH_DW + 2; + /* + * Bspec vol 1c.5 - video engine command streamer: + * "If ENABLED, all TLBs will be invalidated once the flush + * operation is complete. This bit is only valid when the + * Post-Sync Operation field is a value of 1h or 3h." + */ + if (invalidate & I915_GEM_GPU_DOMAINS) + cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD | + MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW; + intel_ring_emit(ring, cmd); + intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT); + intel_ring_emit(ring, 0); /* upper addr */ + intel_ring_emit(ring, 0); /* value */ + intel_ring_emit(ring, 0); /* value */ + intel_ring_emit(ring, MI_NOOP); intel_ring_advance(ring); return 0; } @@ -2029,8 +2055,38 @@ gen6_ring_dispatch_execbuffer(struct intel_engine_cs *ring, return 0; } -/* Blitter support (SandyBridge+) */ +static int gen8_ring_flush(struct intel_engine_cs *ring, + u32 invalidate, u32 flush) +{ + uint32_t cmd; + int ret; + + ret = intel_ring_begin(ring, 6); + if (ret) + return ret; + + cmd = MI_FLUSH_DW + 2; + /* + * Bspec vol 1c.3 - blitter engine command streamer: + * "If ENABLED, all TLBs will be invalidated once the flush + * operation is complete. This bit is only valid when the + * Post-Sync Operation field is a value of 1h or 3h." + */ + if (invalidate & I915_GEM_DOMAIN_RENDER) + cmd |= MI_INVALIDATE_TLB | MI_FLUSH_DW_STORE_INDEX | + MI_FLUSH_DW_OP_STOREDW; + intel_ring_emit(ring, cmd); + intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT); + intel_ring_emit(ring, 0); /* upper addr */ + intel_ring_emit(ring, 0); /* value */ + intel_ring_emit(ring, 0); /* value */ + intel_ring_emit(ring, MI_NOOP); + intel_ring_advance(ring); + + return 0; +} +/* Blitter support (SandyBridge+) */ static int gen6_ring_flush(struct intel_engine_cs *ring, u32 invalidate, u32 flush) { @@ -2043,8 +2099,7 @@ static int gen6_ring_flush(struct intel_engine_cs *ring, return ret; cmd = MI_FLUSH_DW; - if (INTEL_INFO(ring->dev)->gen >= 8) - cmd += 1; + /* * Bspec vol 1c.3 - blitter engine command streamer: * "If ENABLED, all TLBs will be invalidated once the flush @@ -2056,13 +2111,8 @@ static int gen6_ring_flush(struct intel_engine_cs *ring, MI_FLUSH_DW_OP_STOREDW; intel_ring_emit(ring, cmd); intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT); - if (INTEL_INFO(ring->dev)->gen >= 8) { - intel_ring_emit(ring, 0); /* upper addr */ - intel_ring_emit(ring, 0); /* value */ - } else { - intel_ring_emit(ring, 0); - intel_ring_emit(ring, MI_NOOP); - } + intel_ring_emit(ring, 0); + intel_ring_emit(ring, MI_NOOP); intel_ring_advance(ring); if (IS_GEN7(dev) && !invalidate && flush) @@ -2314,6 +2364,7 @@ int intel_init_bsd_ring_buffer(struct drm_device *dev) if (INTEL_INFO(dev)->gen >= 8) { ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT; + ring->flush = gen8_bsd_ring_flush; ring->irq_get = gen8_ring_get_irq; ring->irq_put = gen8_ring_put_irq; ring->dispatch_execbuffer = @@ -2422,6 +2473,7 @@ int intel_init_blt_ring_buffer(struct drm_device *dev) if (INTEL_INFO(dev)->gen >= 8) { ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT; + ring->flush = gen8_ring_flush; ring->irq_get = gen8_ring_get_irq; ring->irq_put = gen8_ring_put_irq; ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer; @@ -2480,6 +2532,7 @@ int intel_init_vebox_ring_buffer(struct drm_device *dev) if (INTEL_INFO(dev)->gen >= 8) { ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT; + ring->flush = gen8_ring_flush; ring->irq_get = gen8_ring_get_irq; ring->irq_put = gen8_ring_put_irq; ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;