From patchwork Thu Aug 7 13:10:02 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: vandana.kannan@intel.com X-Patchwork-Id: 4691071 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 6A11D9F37E for ; Thu, 7 Aug 2014 12:59:02 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 910BC201CE for ; Thu, 7 Aug 2014 12:59:01 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 8957E200F3 for ; Thu, 7 Aug 2014 12:59:00 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id E871F6E77D; Thu, 7 Aug 2014 05:58:59 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by gabe.freedesktop.org (Postfix) with ESMTP id 9EABC6E77D for ; Thu, 7 Aug 2014 05:58:58 -0700 (PDT) Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga103.fm.intel.com with ESMTP; 07 Aug 2014 05:51:46 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.01,818,1400050800"; d="scan'208";a="573100512" Received: from vkannan-desktop.iind.intel.com ([10.223.25.137]) by fmsmga001.fm.intel.com with ESMTP; 07 Aug 2014 05:57:28 -0700 From: Vandana Kannan To: intel-gfx@lists.freedesktop.org Date: Thu, 7 Aug 2014 18:40:02 +0530 Message-Id: <1407417003-10564-2-git-send-email-vandana.kannan@intel.com> X-Mailer: git-send-email 2.0.1 In-Reply-To: <1407417003-10564-1-git-send-email-vandana.kannan@intel.com> References: <20140805154037.GO4193@intel.com> <1407417003-10564-1-git-send-email-vandana.kannan@intel.com> Subject: [Intel-gfx] [PATCH v2 2/3] drm/i915: Get CZ clock for VLV X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP CZ clock is related to data flow from memory to display plane. This is required for comparison with CD clock before programming PFI credits. v2: Ville's review comments - Re-ordered CCK_CZ_CONTROL - Refactored get_clock_speed Signed-off-by: Vandana Kannan --- drivers/gpu/drm/i915/i915_drv.h | 2 ++ drivers/gpu/drm/i915/i915_reg.h | 1 + drivers/gpu/drm/i915/intel_display.c | 43 ++++++++++++++++++++++++++++++------ 3 files changed, 39 insertions(+), 7 deletions(-) Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index dccd0a2..881e0a6 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -2784,6 +2784,8 @@ void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); int vlv_gpu_freq(struct drm_i915_private *dev_priv, int val); int vlv_freq_opcode(struct drm_i915_private *dev_priv, int val); +int valleyview_get_cz_clock_speed(struct drm_device *dev); + #define FORCEWAKE_RENDER (1 << 0) #define FORCEWAKE_MEDIA (1 << 1) #define FORCEWAKE_ALL (FORCEWAKE_RENDER | FORCEWAKE_MEDIA) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index a8275b7..fb111cd 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -616,6 +616,7 @@ enum punit_power_well { #define DSI_PLL_N1_DIV_MASK (3 << 16) #define DSI_PLL_M1_DIV_SHIFT 0 #define DSI_PLL_M1_DIV_MASK (0x1ff << 0) +#define CCK_CZ_CONTROL 0x62 #define CCK_DISPLAY_CLOCK_CONTROL 0x6b #define CCK_TRUNK_FORCE_ON (1 << 17) #define CCK_TRUNK_FORCE_OFF (1 << 16) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index f1f1b54..2089319 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -5316,30 +5316,59 @@ static int intel_crtc_compute_config(struct intel_crtc *crtc, return 0; } -static int valleyview_get_display_clock_speed(struct drm_device *dev) +enum disp_clk { + CDCLK, + CZCLK +}; + +static int valleyview_get_cck_clock_speed(struct drm_device *dev, + enum disp_clk clk) { struct drm_i915_private *dev_priv = dev->dev_private; int vco = valleyview_get_vco(dev_priv); - u32 val; + u32 val, reg; int divider; - /* FIXME: Punit isn't quite ready yet */ - if (IS_CHERRYVIEW(dev)) - return 400000; + switch(clk) { + case CDCLK: + default: + reg = CCK_DISPLAY_CLOCK_CONTROL; + break; + case CZCLK: + reg = CCK_CZ_CONTROL; + break; + } + mutex_lock(&dev_priv->dpio_lock); - val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL); + val = vlv_cck_read(dev_priv, reg); mutex_unlock(&dev_priv->dpio_lock); divider = val & CCK_FREQUENCY_VALUES; WARN((val & CCK_FREQUENCY_STATUS) != (divider << CCK_FREQUENCY_STATUS_SHIFT), - "cdclk change in progress\n"); + "%sclk change in progress\n", (clk == CDCLK) ? "cd" : "cz"); return DIV_ROUND_CLOSEST(vco << 1, divider + 1); } +static int valleyview_get_display_clock_speed(struct drm_device *dev) +{ + /* FIXME: Punit isn't quite ready yet */ + if (IS_CHERRYVIEW(dev)) + return 400000; + else + return valleyview_get_cck_clock_speed(dev, CDCLK); +} + +int valleyview_get_cz_clock_speed(struct drm_device *dev) +{ + return valleyview_get_cck_clock_speed(dev, CZCLK); +} + static int i945_get_display_clock_speed(struct drm_device *dev) { return 400000; -- 2.0.1 _______________________________________________