From patchwork Thu Aug 7 13:10:03 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: vandana.kannan@intel.com X-Patchwork-Id: 4691091 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 1CC7D9F37E for ; Thu, 7 Aug 2014 12:59:04 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 0CD97200F3 for ; Thu, 7 Aug 2014 12:59:03 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id D0D52201DC for ; Thu, 7 Aug 2014 12:59:01 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id CF5DC6E77F; Thu, 7 Aug 2014 05:59:00 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTP id 0BE7A6E77B for ; Thu, 7 Aug 2014 05:58:59 -0700 (PDT) Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga102.fm.intel.com with ESMTP; 07 Aug 2014 05:58:58 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.01,818,1400050800"; d="scan'208";a="573100516" Received: from vkannan-desktop.iind.intel.com ([10.223.25.137]) by fmsmga001.fm.intel.com with ESMTP; 07 Aug 2014 05:57:30 -0700 From: Vandana Kannan To: intel-gfx@lists.freedesktop.org Date: Thu, 7 Aug 2014 18:40:03 +0530 Message-Id: <1407417003-10564-3-git-send-email-vandana.kannan@intel.com> X-Mailer: git-send-email 2.0.1 In-Reply-To: <1407417003-10564-1-git-send-email-vandana.kannan@intel.com> References: <20140805154037.GO4193@intel.com> <1407417003-10564-1-git-send-email-vandana.kannan@intel.com> Cc: Vidya Srinivas Subject: [Intel-gfx] [PATCH 3/3] drm/i915: Program PFI credits for VLV X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Vidya Srinivas PFI credit programming is required when CD clock (related to data flow from display pipeline to end display) is greater than CZ clock (related to data flow from memory to display plane). This programming should be done when all planes are OFF to avoid intermittent hangs while accessing memory even from different Gfx units (not just display). If cdclk/czclk >=1, PFI credits could be set as any number. To get better performance, larger PFI credit can be assigned to PND. Otherwise if cdclk/czclk<1, the default PFI credit of 8 should be set. v2: - Change log to lower log level instead of DRM_ERROR - Change function name to valleyview_program_pfi_credits - Move program PFI credits to modeset_init instead of intel_set_mode - Change magic numbers to logical constants Signed-off-by: Vidya Srinivas Signed-off-by: Gajanan Bhat Signed-off-by: Vandana Kannan --- drivers/gpu/drm/i915/i915_drv.c | 6 ++++++ drivers/gpu/drm/i915/i915_drv.h | 2 ++ drivers/gpu/drm/i915/i915_reg.h | 5 +++++ drivers/gpu/drm/i915/intel_display.c | 4 +++- drivers/gpu/drm/i915/intel_pm.c | 22 ++++++++++++++++++++++ 5 files changed, 38 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index 6c4b25c..00e0b4a 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -558,6 +558,9 @@ static int i915_drm_freeze(struct drm_device *dev) intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED); console_unlock(); + if (IS_VALLEYVIEW(dev)) + valleyview_program_pfi_credits(dev_priv, false); + dev_priv->suspend_count++; intel_display_set_init_power(dev_priv, false); @@ -693,6 +696,9 @@ static int __i915_drm_thaw(struct drm_device *dev, bool restore_gtt_mappings) dev_priv->modeset_restore = MODESET_DONE; mutex_unlock(&dev_priv->modeset_restore_lock); + if (IS_VALLEYVIEW(dev)) + valleyview_program_pfi_credits(dev_priv, true); + intel_opregion_notify_adapter(dev, PCI_D0); return 0; diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 881e0a6..88fd4c7 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -2172,6 +2172,8 @@ extern struct i915_params i915 __read_mostly; /* i915_dma.c */ void i915_update_dri1_breadcrumb(struct drm_device *dev); +extern void valleyview_program_pfi_credits(struct drm_i915_private *dev_priv, + bool flag); extern void i915_kernel_lost_context(struct drm_device * dev); extern int i915_driver_load(struct drm_device *, unsigned long flags); extern int i915_driver_unload(struct drm_device *); diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index fb111cd..7f4c2f5 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1937,6 +1937,11 @@ enum punit_power_well { #define CZCLK_FREQ_MASK 0xf #define GMBUSFREQ_VLV (VLV_DISPLAY_BASE + 0x6510) +#define GCI_CONTROL (VLV_DISPLAY_BASE + 0x650C) +#define PFI_CREDIT (7 << 28) +#define PFI_CREDIT_RESEND (1 << 27) +#define VGA_FAST_MODE_DISABLE (1 << 14) + /* * Palette regs */ diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 2089319..2af2e60 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -12691,8 +12691,10 @@ void intel_modeset_init_hw(struct drm_device *dev) { intel_prepare_ddi(dev); - if (IS_VALLEYVIEW(dev)) + if (IS_VALLEYVIEW(dev)) { vlv_update_cdclk(dev); + valleyview_program_pfi_credits(dev->dev_private, true); + } intel_init_clock_gating(dev); diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index ba8dfeb..ad8e190 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -7154,6 +7154,28 @@ void intel_fini_runtime_pm(struct drm_i915_private *dev_priv) pm_runtime_disable(device); } +void valleyview_program_pfi_credits(struct drm_i915_private *dev_priv, + bool flag) +{ + int cd_clk, cz_clk; + + if (!flag) { + I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE); + return; + } + + cd_clk = dev_priv->display.get_display_clock_speed(dev_priv->dev); + cz_clk = valleyview_get_cz_clock_speed(dev_priv->dev); + + if (cd_clk >= cz_clk) { + /* WA - write default credits before re-programming */ + I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE); + I915_WRITE(GCI_CONTROL, (PFI_CREDIT | PFI_CREDIT_RESEND | + VGA_FAST_MODE_DISABLE)); + } else + DRM_DEBUG_KMS("cd clk < cz clk"); +} + /* Set up chip specific power management-related functions */ void intel_init_pm(struct drm_device *dev) {