From patchwork Mon Sep 1 13:28:53 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: arun.siluvery@linux.intel.com X-Patchwork-Id: 4819471 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 78100C0338 for ; Mon, 1 Sep 2014 13:29:23 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 43FA820131 for ; Mon, 1 Sep 2014 13:29:22 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id D395220154 for ; Mon, 1 Sep 2014 13:29:20 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 5405D6E2FB; Mon, 1 Sep 2014 06:29:20 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTP id A65E46E2FB for ; Mon, 1 Sep 2014 06:29:18 -0700 (PDT) Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga101.fm.intel.com with ESMTP; 01 Sep 2014 06:29:18 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.04,442,1406617200"; d="scan'208";a="584585436" Received: from asiluver-linux.isw.intel.com ([10.102.226.49]) by fmsmga001.fm.intel.com with ESMTP; 01 Sep 2014 06:29:17 -0700 From: Arun Siluvery To: intel-gfx@lists.freedesktop.org Date: Mon, 1 Sep 2014 14:28:53 +0100 Message-Id: <1409578133-2800-5-git-send-email-arun.siluvery@linux.intel.com> X-Mailer: git-send-email 2.0.4 In-Reply-To: <1409578133-2800-1-git-send-email-arun.siluvery@linux.intel.com> References: <1409578133-2800-1-git-send-email-arun.siluvery@linux.intel.com> Subject: [Intel-gfx] [PATCH 4/4] drm/i915: Rework workaround data exporting to debugfs X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-5.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Now w/a are organized in an array so we know exactly how many of them are applied; use the same array while exporting data to debugfs and remove the temporary array we currently have in driver priv structure. Signed-off-by: Arun Siluvery --- drivers/gpu/drm/i915/i915_debugfs.c | 41 +++++++++++++++++++++++---------- drivers/gpu/drm/i915/i915_drv.h | 14 ----------- drivers/gpu/drm/i915/intel_ringbuffer.c | 15 ++++++++++++ drivers/gpu/drm/i915/intel_ringbuffer.h | 8 +++++++ 4 files changed, 52 insertions(+), 26 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index 2727bda..bab0408 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -2465,6 +2465,14 @@ static int i915_wa_registers(struct seq_file *m, void *unused) struct drm_info_node *node = (struct drm_info_node *) m->private; struct drm_device *dev = node->minor->dev; struct drm_i915_private *dev_priv = dev->dev_private; + struct intel_ring_context_rodata ro_data; + + ret = ring_context_rodata(dev, &ro_data); + if (ret) { + seq_printf(m, "Workarounds applied: 0\n"); + DRM_DEBUG_DRIVER("Workaround table not available !!\n"); + return -EINVAL; + } ret = mutex_lock_interruptible(&dev->struct_mutex); if (ret) @@ -2472,18 +2480,27 @@ static int i915_wa_registers(struct seq_file *m, void *unused) intel_runtime_pm_get(dev_priv); - seq_printf(m, "Workarounds applied: %d\n", dev_priv->num_wa_regs); - for (i = 0; i < dev_priv->num_wa_regs; ++i) { - u32 addr, mask; - - addr = dev_priv->intel_wa_regs[i].addr; - mask = dev_priv->intel_wa_regs[i].mask; - dev_priv->intel_wa_regs[i].value = I915_READ(addr) | mask; - if (dev_priv->intel_wa_regs[i].addr) - seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X\n", - dev_priv->intel_wa_regs[i].addr, - dev_priv->intel_wa_regs[i].value, - dev_priv->intel_wa_regs[i].mask); + seq_printf(m, "Workarounds applied: %d\n", ro_data.num_items/2); + for (i = 0; i < ro_data.num_items; i += 2) { + u32 addr, mask, value; + + addr = ro_data.init_context[i]; + /* + * Most of workarounds are masked registers; + * to set a bit in lower 16-bits we set a mask bit in + * upper 16-bits so we can take either of them as mask but + * it doesn't work if the w/a is about clearing a bit so + * use upper 16-bits to cover both cases. + */ + mask = ro_data.init_context[i+1] >> 16; + + /* + * value represents the status of other bits in the + * register besides w/a bits + */ + value = I915_READ(addr) | mask; + seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X\n", + addr, value, mask); } intel_runtime_pm_put(dev_priv); diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 49b7be7..bcf79f0 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1553,20 +1553,6 @@ struct drm_i915_private { struct intel_shared_dpll shared_dplls[I915_NUM_PLLS]; int dpio_phy_iosf_port[I915_NUM_PHYS_VLV]; - /* - * workarounds are currently applied at different places and - * changes are being done to consolidate them so exact count is - * not clear at this point, use a max value for now. - */ -#define I915_MAX_WA_REGS 16 - struct { - u32 addr; - u32 value; - /* bitmask representing WA bits */ - u32 mask; - } intel_wa_regs[I915_MAX_WA_REGS]; - u32 num_wa_regs; - /* Reclocking support */ bool render_reclock_avail; bool lvds_downclock_avail; diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index bae1527..6c07e69 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -760,6 +760,21 @@ static int ring_init_context(struct intel_engine_cs *ring) return ret; } +int ring_context_rodata(struct drm_device *dev, + struct intel_ring_context_rodata *ro_data) +{ + if (IS_CHERRYVIEW(dev)) { + ro_data->init_context = chv_ring_init_context; + ro_data->num_items = ARRAY_SIZE(chv_ring_init_context); + } else if (IS_BROADWELL(dev)) { + ro_data->init_context = bdw_ring_init_context; + ro_data->num_items = ARRAY_SIZE(bdw_ring_init_context); + } else + return -EINVAL; + + return 0; +} + static int init_render_ring(struct intel_engine_cs *ring) { struct drm_device *dev = ring->dev; diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h index 96479c8..f555505 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.h +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h @@ -317,6 +317,14 @@ struct intel_engine_cs { u32 (*get_cmd_length_mask)(u32 cmd_header); }; +struct intel_ring_context_rodata { + u32 num_items; + const u32 *init_context; +}; + +int ring_context_rodata(struct drm_device *dev, + struct intel_ring_context_rodata *ro_data); + bool intel_ring_initialized(struct intel_engine_cs *ring); static inline unsigned