From patchwork Tue Sep 9 14:43:21 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gustavo Padovan X-Patchwork-Id: 4870401 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id AF8D6C033A for ; Tue, 9 Sep 2014 14:43:38 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id EB56920172 for ; Tue, 9 Sep 2014 14:43:33 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 9A64620149 for ; Tue, 9 Sep 2014 14:43:32 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 2294E6E162; Tue, 9 Sep 2014 07:43:32 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-qg0-f48.google.com (mail-qg0-f48.google.com [209.85.192.48]) by gabe.freedesktop.org (Postfix) with ESMTP id 6AE436E162; Tue, 9 Sep 2014 07:43:31 -0700 (PDT) Received: by mail-qg0-f48.google.com with SMTP id q108so236690qgd.21 for ; Tue, 09 Sep 2014 07:43:31 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=+lwtplM8ns3eWN69G9b5vTVA85g7SRjw01bIIAh7ZYQ=; b=Yk3DBjpj6gYGRHx4VfEfKK4KPcVDXazk8qgpCFYsftqI/QlEQ0VHDTl3a4md+6IAsQ SJhn6O0ezHwPzepGjkxwdQPL7zfBH8AvX7wVEAwRvZKVjfHTq0guQCaiWA2iuxbl5ih1 lp/pg0FrtAUxX/XMU2JuQbg1fPWxliC97sw83ZVzP+sMK9fm56kDD5T2P57vk+IV0Hek r+f8G2QzlMv7TvsCyARKd3XEYouZGguIERqYVHRTDs2MmnkY124pdM8vORxN7rUuc8vs c/rWc1Ef4cMMT2Sy6fYMn1EfDinxnqD3XWMdHf7DjuK0ZDDSwnJtDkaFUiLp8Srhjbh2 ANTA== X-Received: by 10.140.104.69 with SMTP id z63mr50189143qge.81.1410273810968; Tue, 09 Sep 2014 07:43:30 -0700 (PDT) Received: from localhost.localdomain ([179.110.36.38]) by mx.google.com with ESMTPSA id g1sm10434647qab.49.2014.09.09.07.43.28 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 09 Sep 2014 07:43:30 -0700 (PDT) From: Gustavo Padovan To: intel-gfx@lists.freedesktop.org Date: Tue, 9 Sep 2014 11:43:21 -0300 Message-Id: <1410273801-20300-3-git-send-email-gustavo@padovan.org> X-Mailer: git-send-email 1.9.3 In-Reply-To: <1410273801-20300-1-git-send-email-gustavo@padovan.org> References: <1410273801-20300-1-git-send-email-gustavo@padovan.org> Cc: Gustavo Padovan , dri-devel@lists.freedesktop.org Subject: [Intel-gfx] [RFC 3/3] drm/i915: Merge of visible and !visible paths for primary planes X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-6.7 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Gustavo Padovan Fold intel_pipe_set_base() in the update primary plane path merging pieces of code that are common to both paths. Basically the the pin/unpin procedures are the same for both paths and some checks can also be shared (some of the were moved to the check() stage) Signed-off-by: Gustavo Padovan --- drivers/gpu/drm/i915/intel_display.c | 100 ++++++++++++++++++++++++----------- 1 file changed, 69 insertions(+), 31 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index e7e7184..175a284 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -11821,16 +11821,36 @@ intel_check_primary_plane(struct drm_plane *plane, struct intel_plane_state *state) { struct drm_crtc *crtc = state->crtc; + struct intel_crtc *intel_crtc = to_intel_crtc(crtc); + struct drm_device *dev = crtc->dev; struct drm_framebuffer *fb = state->fb; struct drm_rect *dest = &state->dst; struct drm_rect *src = &state->src; const struct drm_rect *clip = &state->clip; + int ret; - return drm_plane_helper_check_update(plane, crtc, fb, + ret = drm_plane_helper_check_update(plane, crtc, fb, src, dest, clip, DRM_PLANE_HELPER_NO_SCALING, DRM_PLANE_HELPER_NO_SCALING, false, true, &state->visible); + if (ret) + return ret; + + if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) { + DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n", + plane_name(intel_crtc->plane), + INTEL_INFO(dev)->num_pipes); + return -EINVAL; + } + + /* no fb bound */ + if (state->visible && !fb) { + DRM_ERROR("No FB bound\n"); + return -EINVAL; + } + + return 0; } static int @@ -11842,14 +11862,34 @@ intel_commit_primary_plane(struct drm_plane *plane, struct drm_device *dev = crtc->dev; struct drm_i915_private *dev_priv = dev->dev_private; struct intel_crtc *intel_crtc = to_intel_crtc(crtc); + enum pipe pipe = intel_crtc->pipe; + struct drm_framebuffer *old_fb = plane->fb; struct drm_i915_gem_object *obj = intel_fb_obj(fb); struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb); struct intel_plane *intel_plane = to_intel_plane(plane); struct drm_rect *src = &state->src; - int ret; + int ret = 0; intel_crtc_wait_for_pending_flips(crtc); + if (intel_crtc_has_pending_flip(crtc)) { + DRM_ERROR("pipe is still busy with an old pageflip\n"); + return -EBUSY; + } + + mutex_lock(&dev->struct_mutex); + if (plane->fb != fb) { + ret = intel_pin_and_fence_fb_obj(dev, obj, NULL); + if (ret == 0) + i915_gem_track_fb(old_obj, obj, + INTEL_FRONTBUFFER_PRIMARY(pipe)); + } + mutex_unlock(&dev->struct_mutex); + if (ret != 0) { + DRM_ERROR("pin & fence failed\n"); + return ret; + } + /* * If clipping results in a non-visible primary plane, we'll disable * the primary plane. Note that this is a bit different than what @@ -11857,33 +11897,9 @@ intel_commit_primary_plane(struct drm_plane *plane, * because plane->fb still gets set and pinned. */ if (!state->visible) { - mutex_lock(&dev->struct_mutex); - - /* - * Try to pin the new fb first so that we can bail out if we - * fail. - */ - if (plane->fb != fb) { - ret = intel_pin_and_fence_fb_obj(dev, obj, NULL); - if (ret) { - mutex_unlock(&dev->struct_mutex); - return ret; - } - } - - i915_gem_track_fb(old_obj, obj, - INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe)); - if (intel_crtc->primary_enabled) intel_disable_primary_hw_plane(plane, crtc); - - if (plane->fb != fb) - if (plane->fb) - intel_unpin_fb_obj(old_obj); - - mutex_unlock(&dev->struct_mutex); - } else { if (intel_crtc && intel_crtc->active && intel_crtc->primary_enabled) { @@ -11903,12 +11919,34 @@ intel_commit_primary_plane(struct drm_plane *plane, intel_disable_fbc(dev); } } - ret = intel_pipe_set_base(crtc, src->x1, src->y1, fb); - if (ret) - return ret; - if (!intel_crtc->primary_enabled) - intel_enable_primary_hw_plane(plane, crtc); + intel_update_pipe_size(crtc); + + intel_crtc->primary_enabled = true; + + dev_priv->display.update_primary_plane(crtc, fb, src->x1, src->y1); + + mutex_lock(&dev->struct_mutex); + intel_update_fbc(dev); + mutex_unlock(&dev->struct_mutex); + } + + crtc->primary->fb = fb; + crtc->x = src->x1; + crtc->y = src->y1; + + if (intel_crtc->active) + intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_PRIMARY(pipe)); + + if (old_fb) { + if (intel_crtc->active && old_fb != fb) + intel_wait_for_vblank(dev, intel_crtc->pipe); + + if (old_fb != fb) { + mutex_lock(&dev->struct_mutex); + intel_unpin_fb_obj(old_obj); + mutex_unlock(&dev->struct_mutex); + } } intel_plane->crtc_x = state->orig_dst.x1;