From patchwork Tue Sep 9 19:34:40 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gustavo Padovan X-Patchwork-Id: 4872721 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 48F409F371 for ; Tue, 9 Sep 2014 19:34:55 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 43DD02017A for ; Tue, 9 Sep 2014 19:34:54 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id E2BDC20123 for ; Tue, 9 Sep 2014 19:34:52 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 021496E3BE; Tue, 9 Sep 2014 12:34:52 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-qc0-f173.google.com (mail-qc0-f173.google.com [209.85.216.173]) by gabe.freedesktop.org (Postfix) with ESMTP id 38E4B6E39B; Tue, 9 Sep 2014 12:34:50 -0700 (PDT) Received: by mail-qc0-f173.google.com with SMTP id w7so17919307qcr.18 for ; Tue, 09 Sep 2014 12:34:49 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=8YD/zMotVrcmTOlk28fWl2ztTJRDmHjlzJW3TqVjX3E=; b=CfMwzgOm4vWe9v0Ny46oILGHDbhwBVIsXdI/RLpW+hjrxSX9p1yGlph61+J0rZV6Z+ 1qCoYu9ydHvC2MyThyq3RpAPMr2QT2mUS3R5bKVySqsSd/Gz+J6FLCVFnYfBBAtg5zHc vUQzTAD4KZi6/Ig6pWRptIyKq4I+wuTXRoag3il2IqjotxFg2GvPctk2W4C0KaDR7Cd/ +/2PS+OZUdUfhpYBBbDZSVnimuCnyG3/bxVPuqglDE2H19qMiK15VzJPqa0SoBH0ti3Z rdMa6l4JlvY3mj4fL13wTd5jLsl1zQPZQT+qaGmDgOfh0nY2ybMSr735p7tslDiqGtnJ L94A== X-Received: by 10.224.103.65 with SMTP id j1mr55174492qao.17.1410291289730; Tue, 09 Sep 2014 12:34:49 -0700 (PDT) Received: from localhost.localdomain ([179.110.36.38]) by mx.google.com with ESMTPSA id r7sm3678868qai.15.2014.09.09.12.34.47 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 09 Sep 2014 12:34:49 -0700 (PDT) From: Gustavo Padovan To: intel-gfx@lists.freedesktop.org Date: Tue, 9 Sep 2014 16:34:40 -0300 Message-Id: <1410291280-19495-3-git-send-email-gustavo@padovan.org> X-Mailer: git-send-email 1.9.3 In-Reply-To: <1410291280-19495-1-git-send-email-gustavo@padovan.org> References: <1410291280-19495-1-git-send-email-gustavo@padovan.org> Cc: Gustavo Padovan , dri-devel@lists.freedesktop.org Subject: [Intel-gfx] [PATCH 3/3] drm/i915: Merge of visible and !visible paths for primary planes X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-6.7 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Gustavo Padovan Fold intel_pipe_set_base() in the update primary plane path merging pieces of code that are common to both paths. Basically the the pin/unpin procedures are the same for both paths and some checks can also be shared (some of the were moved to the check() stage) v2: take Ville's comments: - remove unecessary plane check - move mutex lock to inside the conditional - make the pin fail message a debug one - add a fixme for the fastboot hack - call intel_frontbuffer_flip() after FBC update Signed-off-by: Gustavo Padovan --- drivers/gpu/drm/i915/intel_display.c | 93 ++++++++++++++++++++++++------------ 1 file changed, 62 insertions(+), 31 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 0e03fee..68d7625 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -11825,12 +11825,23 @@ intel_check_primary_plane(struct drm_plane *plane, struct drm_rect *dest = &state->dst; struct drm_rect *src = &state->src; const struct drm_rect *clip = &state->clip; + int ret; - return drm_plane_helper_check_update(plane, crtc, fb, + ret = drm_plane_helper_check_update(plane, crtc, fb, src, dest, clip, DRM_PLANE_HELPER_NO_SCALING, DRM_PLANE_HELPER_NO_SCALING, false, true, &state->visible); + if (ret) + return ret; + + /* no fb bound */ + if (state->visible && !fb) { + DRM_ERROR("No FB bound\n"); + return -EINVAL; + } + + return 0; } static int @@ -11842,14 +11853,34 @@ intel_commit_primary_plane(struct drm_plane *plane, struct drm_device *dev = crtc->dev; struct drm_i915_private *dev_priv = dev->dev_private; struct intel_crtc *intel_crtc = to_intel_crtc(crtc); + enum pipe pipe = intel_crtc->pipe; + struct drm_framebuffer *old_fb = plane->fb; struct drm_i915_gem_object *obj = intel_fb_obj(fb); struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb); struct intel_plane *intel_plane = to_intel_plane(plane); struct drm_rect *src = &state->src; - int ret; + int ret = 0; intel_crtc_wait_for_pending_flips(crtc); + if (intel_crtc_has_pending_flip(crtc)) { + DRM_ERROR("pipe is still busy with an old pageflip\n"); + return -EBUSY; + } + + if (plane->fb != fb) { + mutex_lock(&dev->struct_mutex); + ret = intel_pin_and_fence_fb_obj(dev, obj, NULL); + if (ret == 0) + i915_gem_track_fb(old_obj, obj, + INTEL_FRONTBUFFER_PRIMARY(pipe)); + mutex_unlock(&dev->struct_mutex); + } + if (ret != 0) { + DRM_DEBUG_KMS("pin & fence failed\n"); + return ret; + } + /* * If clipping results in a non-visible primary plane, we'll disable * the primary plane. Note that this is a bit different than what @@ -11857,33 +11888,9 @@ intel_commit_primary_plane(struct drm_plane *plane, * because plane->fb still gets set and pinned. */ if (!state->visible) { - mutex_lock(&dev->struct_mutex); - - /* - * Try to pin the new fb first so that we can bail out if we - * fail. - */ - if (plane->fb != fb) { - ret = intel_pin_and_fence_fb_obj(dev, obj, NULL); - if (ret) { - mutex_unlock(&dev->struct_mutex); - return ret; - } - } - - i915_gem_track_fb(old_obj, obj, - INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe)); - if (intel_crtc->primary_enabled) intel_disable_primary_hw_plane(plane, crtc); - - if (plane->fb != fb) - if (plane->fb) - intel_unpin_fb_obj(old_obj); - - mutex_unlock(&dev->struct_mutex); - } else { if (intel_crtc && intel_crtc->active && intel_crtc->primary_enabled) { @@ -11903,12 +11910,36 @@ intel_commit_primary_plane(struct drm_plane *plane, intel_disable_fbc(dev); } } - ret = intel_pipe_set_base(crtc, src->x1, src->y1, fb); - if (ret) - return ret; - if (!intel_crtc->primary_enabled) - intel_enable_primary_hw_plane(plane, crtc); + /* FIXME: kill this fastboot hack */ + intel_update_pipe_size(intel_crtc); + + intel_crtc->primary_enabled = true; + + dev_priv->display.update_primary_plane(crtc, fb, src->x1, src->y1); + + if (intel_crtc->active) + intel_frontbuffer_flip(dev, + INTEL_FRONTBUFFER_PRIMARY(pipe)); + + mutex_lock(&dev->struct_mutex); + intel_update_fbc(dev); + mutex_unlock(&dev->struct_mutex); + } + + crtc->primary->fb = fb; + crtc->x = src->x1; + crtc->y = src->y1; + + if (old_fb) { + if (intel_crtc->active && old_fb != fb) + intel_wait_for_vblank(dev, intel_crtc->pipe); + + if (old_fb != fb) { + mutex_lock(&dev->struct_mutex); + intel_unpin_fb_obj(old_obj); + mutex_unlock(&dev->struct_mutex); + } } intel_plane->crtc_x = state->orig_dst.x1;