From patchwork Fri Sep 12 15:10:01 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michel Thierry X-Patchwork-Id: 4895941 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 4208C9F32F for ; Fri, 12 Sep 2014 15:06:33 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 00D4F2010E for ; Fri, 12 Sep 2014 15:11:24 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 70FA8202B4 for ; Fri, 12 Sep 2014 15:11:21 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 0B3DC6E737; Fri, 12 Sep 2014 08:11:21 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTP id 0487C6E737 for ; Fri, 12 Sep 2014 08:11:18 -0700 (PDT) Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga101.jf.intel.com with ESMTP; 12 Sep 2014 08:10:53 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.04,513,1406617200"; d="scan'208";a="602041385" Received: from michelth-linux.isw.intel.com ([10.102.226.151]) by orsmga002.jf.intel.com with ESMTP; 12 Sep 2014 08:09:59 -0700 From: Michel Thierry To: intel-gfx@lists.freedesktop.org Date: Fri, 12 Sep 2014 16:10:01 +0100 Message-Id: <1410534601-11523-1-git-send-email-michel.thierry@intel.com> X-Mailer: git-send-email 2.0.3 Cc: Ben Widawsky , Ben Widawsky Subject: [Intel-gfx] [PATCH] drm/i915/ppgtt: Load address space after mi_set_context X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-6.4 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Ben Widawsky The simple explanation is, the docs say to do this for GEN8. Perhaps we want to do this for GEN7 too, I am not certain. PDPs are saved and restored with context. Contexts (without execlists) only exist on the render ring. The docs say that PDPs are not power context save/restored. I've learned that this actually means something which SW doesn't care about. So pretend the statement doesn't exist. For non RCS, nothing changes. All this patch now does is change the ordering of LRI vs MI_SET_CONTEXT for the initialization of the context. I do this because the docs say to do it, and frankly, I cannot reason why it is necessary. I've thought about it a lot, and tried, without success, to get a reason from design. The answer I got more or less says, "gen7 is different than gen8." I've given up, and am adding this little bit of code to make it in sync with the docs. v2: Completely rewritten commit message that addresses the requests Ville made for v1 Only load PDPs for initial context load (Ville) v3: Rebased after ppgtt clean-up rules, and apply only for render ring. This is needed to boot to desktop with full ppgtt in legacy mode (without execlists). Signed-off-by: Ben Widawsky Signed-off-by: Michel Thierry (v3) --- drivers/gpu/drm/i915/i915_gem_context.c | 31 +++++++++++++++++++++++++++++-- 1 file changed, 29 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c index a5221d8..faebbf3 100644 --- a/drivers/gpu/drm/i915/i915_gem_context.c +++ b/drivers/gpu/drm/i915/i915_gem_context.c @@ -522,6 +522,8 @@ static int do_switch(struct intel_engine_cs *ring, struct intel_context *from = ring->last_context; u32 hw_flags = 0; bool uninitialized = false; + bool needs_pd_load_rcs = (INTEL_INFO(ring->dev)->gen < 8) && to->ppgtt; + bool needs_pd_load_xcs = (ring != &dev_priv->ring[RCS]) && to->ppgtt; int ret, i; if (from != NULL && ring == &dev_priv->ring[RCS]) { @@ -547,7 +549,11 @@ static int do_switch(struct intel_engine_cs *ring, */ from = ring->last_context; - if (to->ppgtt) { + if (needs_pd_load_rcs || needs_pd_load_xcs) { + /* Older GENs and non render rings still want the load first, + * "PP_DCLV followed by PP_DIR_BASE register through Load + * Register Immediate commands in Ring Buffer before submitting + * a context."*/ ret = to->ppgtt->switch_mm(to->ppgtt, ring); if (ret) goto unpin_out; @@ -577,13 +583,34 @@ static int do_switch(struct intel_engine_cs *ring, vma->bind_vma(vma, to->legacy_hw_ctx.rcs_state->cache_level, GLOBAL_BIND); } - if (!to->legacy_hw_ctx.initialized || i915_gem_context_is_default(to)) + if (!to->legacy_hw_ctx.initialized || i915_gem_context_is_default(to)) { hw_flags |= MI_RESTORE_INHIBIT; + needs_pd_load_rcs = to->ppgtt && IS_GEN8(ring->dev); + } ret = mi_set_context(ring, to, hw_flags); if (ret) goto unpin_out; + /* GEN8 does *not* require an explicit reload if the PDPs have been + * setup, and we do not wish to move them. + * + * XXX: If we implemented page directory eviction code, this + * optimization needs to be removed. + */ + if (needs_pd_load_rcs) { + ret = to->ppgtt->switch_mm(to->ppgtt, ring); + /* The hardware context switch is emitted, but we haven't + * actually changed the state - so it's probably safe to bail + * here. Still, let the user know something dangerous has + * happened. + */ + if (ret) { + DRM_ERROR("Failed to change address space on context switch\n"); + goto unpin_out; + } + } + for (i = 0; i < MAX_L3_SLICES; i++) { if (!(to->remap_slice & (1<