From patchwork Wed Sep 24 12:02:12 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michel Thierry X-Patchwork-Id: 4964651 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id B3550BEEA5 for ; Wed, 24 Sep 2014 12:02:38 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id E9CD720155 for ; Wed, 24 Sep 2014 12:02:33 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 5672E2011B for ; Wed, 24 Sep 2014 12:02:32 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 010FD6E292; Wed, 24 Sep 2014 05:02:32 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by gabe.freedesktop.org (Postfix) with ESMTP id 623786E292 for ; Wed, 24 Sep 2014 05:02:28 -0700 (PDT) Received: from azsmga001.ch.intel.com ([10.2.17.19]) by fmsmga103.fm.intel.com with ESMTP; 24 Sep 2014 04:53:00 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.04,588,1406617200"; d="scan'208";a="479684807" Received: from michelth-linux.isw.intel.com ([10.102.226.151]) by azsmga001.ch.intel.com with ESMTP; 24 Sep 2014 05:02:07 -0700 From: Michel Thierry To: intel-gfx@lists.freedesktop.org Date: Wed, 24 Sep 2014 13:02:12 +0100 Message-Id: <1411560132-9086-2-git-send-email-michel.thierry@intel.com> X-Mailer: git-send-email 2.0.3 In-Reply-To: <1411560132-9086-1-git-send-email-michel.thierry@intel.com> References: <1411560132-9086-1-git-send-email-michel.thierry@intel.com> Subject: [Intel-gfx] [PATCH v2 2/2] drm/i915: Initialize chv workarounds in logical ring mode too X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Also enable the ring->init_context() hook for chv in execlist submission mode. For: VIZ-4092 Signed-off-by: Michel Thierry --- drivers/gpu/drm/i915/intel_lrc.c | 37 ++++++++++++++++++++++++++++++- drivers/gpu/drm/i915/intel_ringbuffer.c | 39 +++++++++++++++++++-------------- drivers/gpu/drm/i915/intel_ringbuffer.h | 2 ++ 3 files changed, 61 insertions(+), 17 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c index a0aa3f0..7864dac 100644 --- a/drivers/gpu/drm/i915/intel_lrc.c +++ b/drivers/gpu/drm/i915/intel_lrc.c @@ -1076,6 +1076,39 @@ static int bdw_init_logical_workarounds(struct intel_ringbuffer *ringbuf) return 0; } +static int chv_init_logical_workarounds(struct intel_ringbuffer *ringbuf) +{ + int ret; + struct intel_engine_cs *ring = ringbuf->ring; + struct drm_device *dev = ring->dev; + struct drm_i915_private *dev_priv = dev->dev_private; + + /* + * workarounds applied in this fn are part of register state context, + * they need to be re-initialized followed by gpu reset, suspend/resume, + * module reload. + */ + dev_priv->num_wa_regs = 0; + memset(dev_priv->intel_wa_regs, 0, sizeof(dev_priv->intel_wa_regs)); + + /* + * update the number of dwords required based on the + * actual number of workarounds applied + */ + ret = intel_logical_ring_begin(ringbuf, CHV_WA_DWORDS_SIZE); + if (ret) + return ret; + + chv_emit_workarounds(ringbuf); + + intel_logical_ring_advance(ringbuf); + + DRM_DEBUG_DRIVER("Number of Workarounds applied: %d\n", + dev_priv->num_wa_regs); + + return 0; +} + static int gen8_init_common_ring(struct intel_engine_cs *ring) { struct drm_device *dev = ring->dev; @@ -1371,7 +1404,9 @@ static int logical_render_ring_init(struct drm_device *dev) if (HAS_L3_DPF(dev)) ring->irq_keep_mask |= GT_RENDER_L3_PARITY_ERROR_INTERRUPT; - if (IS_BROADWELL(dev)) + if (IS_CHERRYVIEW(dev)) + ring->init_context = chv_init_logical_workarounds; + else ring->init_context = bdw_init_logical_workarounds; ring->emit_wa = intel_logical_ring_emit_wa; diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index e6ac913..ec0b2f0 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -776,6 +776,27 @@ static int bdw_init_workarounds(struct intel_ringbuffer *ringbuf) return 0; } +void chv_emit_workarounds(struct intel_ringbuffer *ringbuf) +{ + struct intel_engine_cs *ring = ringbuf->ring; + + /* WaDisablePartialInstShootdown:chv */ + ring->emit_wa(ringbuf, GEN8_ROW_CHICKEN, + _MASKED_BIT_ENABLE(PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE)); + + /* WaDisableThreadStallDopClockGating:chv */ + ring->emit_wa(ringbuf, GEN8_ROW_CHICKEN, + _MASKED_BIT_ENABLE(STALL_DOP_GATING_DISABLE)); + + /* WaDisableDopClockGating:chv (pre-production hw) */ + ring->emit_wa(ringbuf, GEN7_ROW_CHICKEN2, + _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); + + /* WaDisableSamplerPowerBypass:chv (pre-production hw) */ + ring->emit_wa(ringbuf, HALF_SLICE_CHICKEN3, + _MASKED_BIT_ENABLE(GEN8_SAMPLER_POWER_BYPASS_DIS)); +} + static int chv_init_workarounds(struct intel_ringbuffer *ringbuf) { int ret; @@ -791,25 +812,11 @@ static int chv_init_workarounds(struct intel_ringbuffer *ringbuf) dev_priv->num_wa_regs = 0; memset(dev_priv->intel_wa_regs, 0, sizeof(dev_priv->intel_wa_regs)); - ret = intel_ring_begin(ring, 12); + ret = intel_ring_begin(ring, CHV_WA_DWORDS_SIZE); if (ret) return ret; - /* WaDisablePartialInstShootdown:chv */ - intel_ring_emit_wa(ringbuf, GEN8_ROW_CHICKEN, - _MASKED_BIT_ENABLE(PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE)); - - /* WaDisableThreadStallDopClockGating:chv */ - intel_ring_emit_wa(ringbuf, GEN8_ROW_CHICKEN, - _MASKED_BIT_ENABLE(STALL_DOP_GATING_DISABLE)); - - /* WaDisableDopClockGating:chv (pre-production hw) */ - intel_ring_emit_wa(ringbuf, GEN7_ROW_CHICKEN2, - _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); - - /* WaDisableSamplerPowerBypass:chv (pre-production hw) */ - intel_ring_emit_wa(ringbuf, HALF_SLICE_CHICKEN3, - _MASKED_BIT_ENABLE(GEN8_SAMPLER_POWER_BYPASS_DIS)); + chv_emit_workarounds(ringbuf); intel_ring_advance(ring); diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h index 417aa09..02e3728 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.h +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h @@ -16,6 +16,7 @@ * actual number of workarounds applied */ #define BDW_WA_DWORDS_SIZE 18 +#define CHV_WA_DWORDS_SIZE 12 /* * Gen2 BSpec "1. Programming Environment" / 1.4.4.6 "Ring Buffer Use" @@ -436,6 +437,7 @@ int intel_init_vebox_ring_buffer(struct drm_device *dev); u64 intel_ring_get_active_head(struct intel_engine_cs *ring); void intel_ring_setup_status_page(struct intel_engine_cs *ring); void bdw_emit_workarounds(struct intel_ringbuffer *ringbuf); +void chv_emit_workarounds(struct intel_ringbuffer *ringbuf); static inline u32 intel_ring_get_tail(struct intel_ringbuffer *ringbuf) {