From patchwork Tue Oct 7 19:11:10 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Paulo Zanoni X-Patchwork-Id: 5048461 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id E657CC11AC for ; Tue, 7 Oct 2014 19:11:38 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id EC9A420220 for ; Tue, 7 Oct 2014 19:11:36 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id CCB232018E for ; Tue, 7 Oct 2014 19:11:35 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 337EA89E38; Tue, 7 Oct 2014 12:11:35 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-qc0-f176.google.com (mail-qc0-f176.google.com [209.85.216.176]) by gabe.freedesktop.org (Postfix) with ESMTP id 5E0E589E38 for ; Tue, 7 Oct 2014 12:11:33 -0700 (PDT) Received: by mail-qc0-f176.google.com with SMTP id r5so6256609qcx.7 for ; Tue, 07 Oct 2014 12:11:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id; bh=uYQGw5CNtxvlIV/z2sj36fN7WKMB4W3n+DY1y4DR0EE=; b=kuLNIfsOYGUFuwHgzZstUAYrI2KL5UjTn9bZf4+Hbey58GSLRnviFQxXQWAPD6YPyU B4GL4XpFQR3Bx8pRUcrJRV/qw+rZp2CZmdr2Szqh7cvUhIJho0+3fuscrwA1W+lwlqom Y40tLh9JFAnZqulweL1r1XyCuUX/HlsBFMPqjaR7zqnq10hwOWRR3eM71NbJeA/PQ436 9njGrJNeObsMcKvrcGnlkadORS7Ye8vOcq/2JyqdA8u0zNBs+kBX2TNe2trp9JZTLKB5 3myH8LGWWs33XfVUsM9Pozpv4mz/JHjr5TvLYbf891RtTCGynyavWcrRJmvAPJUjCBgM TF3Q== X-Received: by 10.224.80.10 with SMTP id r10mr7114624qak.24.1412709092806; Tue, 07 Oct 2014 12:11:32 -0700 (PDT) Received: from localhost.localdomain ([177.40.35.66]) by mx.google.com with ESMTPSA id 33sm15357694qgy.30.2014.10.07.12.11.31 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 07 Oct 2014 12:11:32 -0700 (PDT) From: Paulo Zanoni To: intel-gfx@lists.freedesktop.org Date: Tue, 7 Oct 2014 16:11:10 -0300 Message-Id: <1412709071-1886-1-git-send-email-przanoni@gmail.com> X-Mailer: git-send-email 1.9.1 Cc: Paulo Zanoni , stable@vger.kernel.org Subject: [Intel-gfx] [PATCH 1/2] drm/i915: properly reenable gen8 pipe IRQs X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.1 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_MED, T_DKIM_INVALID, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Paulo Zanoni We were missing the pipe B/C vblank bits! Take a look at gen8_de_irq_postinstall for a comparison. This should fix a bunch of IGT tests. There are a few more things we could improve on this code, but this should be the minimal fix to unblock us. Bugzilla:https://bugs.freedesktop.org/show_bug.cgi?id=83640 Testcase: igt/* Cc: stable@vger.kernel.org Signed-off-by: Paulo Zanoni Reviewed-by: Ville Syrjälä --- drivers/gpu/drm/i915/i915_irq.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index b12c4c4..3bbdb9c 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -3166,11 +3166,13 @@ static void gen8_irq_reset(struct drm_device *dev) void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv) { + uint32_t extra_iir = GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN; + spin_lock_irq(&dev_priv->irq_lock); GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_B, dev_priv->de_irq_mask[PIPE_B], - ~dev_priv->de_irq_mask[PIPE_B]); + ~dev_priv->de_irq_mask[PIPE_B] | extra_iir); GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_C, dev_priv->de_irq_mask[PIPE_C], - ~dev_priv->de_irq_mask[PIPE_C]); + ~dev_priv->de_irq_mask[PIPE_C] | extra_iir); spin_unlock_irq(&dev_priv->irq_lock); }