diff mbox

drm/i915: properly reenable gen8 pipe IRQs

Message ID 1412715772-1884-1-git-send-email-przanoni@gmail.com (mailing list archive)
State New, archived
Headers show

Commit Message

Paulo Zanoni Oct. 7, 2014, 9:02 p.m. UTC 
From: Paulo Zanoni <paulo.r.zanoni@intel.com>

We were missing the pipe B/C vblank bits! Take a look at
gen8_de_irq_postinstall for a comparison.

This should fix a bunch of IGT tests.

There are a few more things we could improve on this code, but this
should be the minimal fix to unblock us.

v2: s/extra_iir/extra_ier/ because IIR doesn't make sense (Ville)

Bugzilla:https://bugs.freedesktop.org/show_bug.cgi?id=83640
Testcase: igt/*
Cc: stable@vger.kernel.org
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
 drivers/gpu/drm/i915/i915_irq.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

Comments

Jani Nikula Oct. 8, 2014, 8:25 a.m. UTC | #1 
On Wed, 08 Oct 2014, Paulo Zanoni <przanoni@gmail.com> wrote:
> From: Paulo Zanoni <paulo.r.zanoni@intel.com>
>
> We were missing the pipe B/C vblank bits! Take a look at
> gen8_de_irq_postinstall for a comparison.
>
> This should fix a bunch of IGT tests.
>
> There are a few more things we could improve on this code, but this
> should be the minimal fix to unblock us.
>
> v2: s/extra_iir/extra_ier/ because IIR doesn't make sense (Ville)
>
> Bugzilla:https://bugs.freedesktop.org/show_bug.cgi?id=83640

Maybe https://bugs.freedesktop.org/show_bug.cgi?id=84217 too, and
others?

BR,
Jani.


> Testcase: igt/*
> Cc: stable@vger.kernel.org
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_irq.c | 6 ++++--
>  1 file changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index b12c4c4..c141ff8 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -3166,11 +3166,13 @@ static void gen8_irq_reset(struct drm_device *dev)
>  
>  void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv)
>  {
> +	uint32_t extra_ier = GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN;
> +
>  	spin_lock_irq(&dev_priv->irq_lock);
>  	GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_B, dev_priv->de_irq_mask[PIPE_B],
> -			  ~dev_priv->de_irq_mask[PIPE_B]);
> +			  ~dev_priv->de_irq_mask[PIPE_B] | extra_ier);
>  	GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_C, dev_priv->de_irq_mask[PIPE_C],
> -			  ~dev_priv->de_irq_mask[PIPE_C]);
> +			  ~dev_priv->de_irq_mask[PIPE_C] | extra_ier);
>  	spin_unlock_irq(&dev_priv->irq_lock);
>  }
>  
> -- 
> 2.1.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Jani Nikula Oct. 8, 2014, 1:49 p.m. UTC | #2 
On Wed, 08 Oct 2014, Paulo Zanoni <przanoni@gmail.com> wrote:
> From: Paulo Zanoni <paulo.r.zanoni@intel.com>
>
> We were missing the pipe B/C vblank bits! Take a look at
> gen8_de_irq_postinstall for a comparison.
>
> This should fix a bunch of IGT tests.
>
> There are a few more things we could improve on this code, but this
> should be the minimal fix to unblock us.
>
> v2: s/extra_iir/extra_ier/ because IIR doesn't make sense (Ville)
>
> Bugzilla:https://bugs.freedesktop.org/show_bug.cgi?id=83640
> Testcase: igt/*
> Cc: stable@vger.kernel.org
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>

Pushed to drm-intel-next-fixes, thanks for the patch and review.

Paulo, please ask for retests on all relevant bug reports.

BR,
Jani.


> ---
>  drivers/gpu/drm/i915/i915_irq.c | 6 ++++--
>  1 file changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index b12c4c4..c141ff8 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -3166,11 +3166,13 @@ static void gen8_irq_reset(struct drm_device *dev)
>  
>  void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv)
>  {
> +	uint32_t extra_ier = GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN;
> +
>  	spin_lock_irq(&dev_priv->irq_lock);
>  	GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_B, dev_priv->de_irq_mask[PIPE_B],
> -			  ~dev_priv->de_irq_mask[PIPE_B]);
> +			  ~dev_priv->de_irq_mask[PIPE_B] | extra_ier);
>  	GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_C, dev_priv->de_irq_mask[PIPE_C],
> -			  ~dev_priv->de_irq_mask[PIPE_C]);
> +			  ~dev_priv->de_irq_mask[PIPE_C] | extra_ier);
>  	spin_unlock_irq(&dev_priv->irq_lock);
>  }
>  
> -- 
> 2.1.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Paulo Zanoni Oct. 8, 2014, 6:36 p.m. UTC | #3 
2014-10-08 5:25 GMT-03:00 Jani Nikula <jani.nikula@linux.intel.com>:
> On Wed, 08 Oct 2014, Paulo Zanoni <przanoni@gmail.com> wrote:
>> From: Paulo Zanoni <paulo.r.zanoni@intel.com>
>>
>> We were missing the pipe B/C vblank bits! Take a look at
>> gen8_de_irq_postinstall for a comparison.
>>
>> This should fix a bunch of IGT tests.
>>
>> There are a few more things we could improve on this code, but this
>> should be the minimal fix to unblock us.
>>
>> v2: s/extra_iir/extra_ier/ because IIR doesn't make sense (Ville)
>>
>> Bugzilla:https://bugs.freedesktop.org/show_bug.cgi?id=83640
>
> Maybe https://bugs.freedesktop.org/show_bug.cgi?id=84217 too, and
> others?

Yeah, I can confirm that this patch fixes at least 84162, 83969, 84217
and 83640 from bugzilla.freedesktop.org on my machine.


>
> BR,
> Jani.
>
>
>> Testcase: igt/*
>> Cc: stable@vger.kernel.org
>> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
>> ---
>>  drivers/gpu/drm/i915/i915_irq.c | 6 ++++--
>>  1 file changed, 4 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
>> index b12c4c4..c141ff8 100644
>> --- a/drivers/gpu/drm/i915/i915_irq.c
>> +++ b/drivers/gpu/drm/i915/i915_irq.c
>> @@ -3166,11 +3166,13 @@ static void gen8_irq_reset(struct drm_device *dev)
>>
>>  void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv)
>>  {
>> +     uint32_t extra_ier = GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN;
>> +
>>       spin_lock_irq(&dev_priv->irq_lock);
>>       GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_B, dev_priv->de_irq_mask[PIPE_B],
>> -                       ~dev_priv->de_irq_mask[PIPE_B]);
>> +                       ~dev_priv->de_irq_mask[PIPE_B] | extra_ier);
>>       GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_C, dev_priv->de_irq_mask[PIPE_C],
>> -                       ~dev_priv->de_irq_mask[PIPE_C]);
>> +                       ~dev_priv->de_irq_mask[PIPE_C] | extra_ier);
>>       spin_unlock_irq(&dev_priv->irq_lock);
>>  }
>>
>> --
>> 2.1.1
>>
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
> --
> Jani Nikula, Intel Open Source Technology Center
diff mbox

Patch

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index b12c4c4..c141ff8 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -3166,11 +3166,13 @@  static void gen8_irq_reset(struct drm_device *dev)
 
 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv)
 {
+	uint32_t extra_ier = GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN;
+
 	spin_lock_irq(&dev_priv->irq_lock);
 	GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_B, dev_priv->de_irq_mask[PIPE_B],
-			  ~dev_priv->de_irq_mask[PIPE_B]);
+			  ~dev_priv->de_irq_mask[PIPE_B] | extra_ier);
 	GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_C, dev_priv->de_irq_mask[PIPE_C],
-			  ~dev_priv->de_irq_mask[PIPE_C]);
+			  ~dev_priv->de_irq_mask[PIPE_C] | extra_ier);
 	spin_unlock_irq(&dev_priv->irq_lock);
 }