From patchwork Thu Oct 9 16:37:12 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Todd Previte X-Patchwork-Id: 5059251 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 216ECC11AC for ; Thu, 9 Oct 2014 16:37:47 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 3BF0620200 for ; Thu, 9 Oct 2014 16:37:46 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 206D3201FE for ; Thu, 9 Oct 2014 16:37:45 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id A66DD6E39C; Thu, 9 Oct 2014 09:37:44 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-pa0-f49.google.com (mail-pa0-f49.google.com [209.85.220.49]) by gabe.freedesktop.org (Postfix) with ESMTP id 31DF46E39C for ; Thu, 9 Oct 2014 09:37:43 -0700 (PDT) Received: by mail-pa0-f49.google.com with SMTP id hz1so78222pad.8 for ; Thu, 09 Oct 2014 09:37:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id; bh=b0PS3g2751grndq9Y5HY1apfbEs0/isllO7Uudj/Ml4=; b=SCFz5xj7dZxHjcR0K6Yjan1DtJSZaYQBCWZySMjOkZWhBuQWVSJ5cwDKnno22rtdLY 6kRknTtJE8NLKtr69Kp/KpElFP3dnPB8frCtddb8iQ4jQ6WjjDsIm6L5HD4r7Y99WVw7 8sfgedO4f6AK3hgrIWf+08xZLR0bcapjxm4JvxTPHUD48qLc+rhpFgusKs1k/lhW/RT6 oEO1ju/YQosjRqWcxEeCMBfOmlTUrPGBjm91UvCfGH+qBwJQfHMCQP5ENACKnZpDd7OV i8A2a8H8nABvR7gjKEVZE2XAYIC/tpNUOo/bow7CD3LMBg+zDweh7CHpYMkznJT2BzPP RFlw== X-Received: by 10.68.216.35 with SMTP id on3mr862135pbc.34.1412872662932; Thu, 09 Oct 2014 09:37:42 -0700 (PDT) Received: from localhost.localdomain (ip72-201-95-47.ph.ph.cox.net. [72.201.95.47]) by mx.google.com with ESMTPSA id x15sm949174pbt.91.2014.10.09.09.37.41 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 09 Oct 2014 09:37:41 -0700 (PDT) From: Todd Previte To: intel-gfx@lists.freedesktop.org Date: Thu, 9 Oct 2014 09:37:12 -0700 Message-Id: <1412872632-49802-1-git-send-email-tprevite@gmail.com> X-Mailer: git-send-email 1.9.1 Subject: [Intel-gfx] [PATCH] drm/i915: Change order of operations for VLV/CHV to not train DP link before PHYs are ready X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.1 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_MED, T_DKIM_INVALID, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Reorder the function calls in chv/vlv_pre_enable_dp() such that link training is not initiated before the PHYs come up out of reset. Also check the status of vlv_wait_port_ready() and only attempt to train if the PHYs are actually running. The specification lists the wait for the PHYs as one of the final steps in enabling the Displayport hardware for use. While the PHYs are in reset, no communication is p ossible across the link. Attempting to train the link while the PHYs are in reset will result in link training failure with one or more WARN() in the logs. Moving the intel_enable_dp() function after vlv_wait_port_ready() and only when the PHYs are ready helps ensure reliable operation of the Displayport link. Signed-off-by: Todd Previte --- drivers/gpu/drm/i915/intel_display.c | 8 ++++++-- drivers/gpu/drm/i915/intel_dp.c | 10 ++++------ drivers/gpu/drm/i915/intel_drv.h | 2 +- 3 files changed, 11 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index c51d950..4b280c1 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -1723,7 +1723,7 @@ static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) mutex_unlock(&dev_priv->dpio_lock); } -void vlv_wait_port_ready(struct drm_i915_private *dev_priv, +int vlv_wait_port_ready(struct drm_i915_private *dev_priv, struct intel_digital_port *dport) { u32 port_mask; @@ -1746,9 +1746,13 @@ void vlv_wait_port_ready(struct drm_i915_private *dev_priv, BUG(); } - if (wait_for((I915_READ(dpll_reg) & port_mask) == 0, 1000)) + if (wait_for((I915_READ(dpll_reg) & port_mask) == 0, 1000)) { WARN(1, "timed out waiting for port %c ready: 0x%08x\n", port_name(dport->port), I915_READ(dpll_reg)); + return -EIO; + } + + return 0; } static void intel_prepare_shared_dpll(struct intel_crtc *crtc) diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index a8352c4..ada8b07 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -2705,9 +2705,8 @@ static void vlv_pre_enable_dp(struct intel_encoder *encoder) pps_unlock(intel_dp); } - intel_enable_dp(encoder); - - vlv_wait_port_ready(dev_priv, dport); + if (vlv_wait_port_ready(dev_priv, dport) == 0) + intel_enable_dp(encoder); } static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder) @@ -2805,9 +2804,8 @@ static void chv_pre_enable_dp(struct intel_encoder *encoder) pps_unlock(intel_dp); } - intel_enable_dp(encoder); - - vlv_wait_port_ready(dev_priv, dport); + if (vlv_wait_port_ready(dev_priv, dport) == 0) + intel_enable_dp(encoder); } static void chv_dp_pre_pll_enable(struct intel_encoder *encoder) diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index dc80444..2ff2c8c 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -876,7 +876,7 @@ intel_wait_for_vblank(struct drm_device *dev, int pipe) drm_wait_one_vblank(dev, pipe); } int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp); -void vlv_wait_port_ready(struct drm_i915_private *dev_priv, +int vlv_wait_port_ready(struct drm_i915_private *dev_priv, struct intel_digital_port *dport); bool intel_get_load_detect_pipe(struct drm_connector *connector, struct drm_display_mode *mode,