From patchwork Mon Oct 20 12:50:07 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: vandana.kannan@intel.com X-Patchwork-Id: 5105281 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id E62F39F374 for ; Mon, 20 Oct 2014 12:36:01 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id E804C201F7 for ; Mon, 20 Oct 2014 12:35:57 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 69000201D3 for ; Mon, 20 Oct 2014 12:35:56 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 414576E044; Mon, 20 Oct 2014 05:35:55 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTP id 5D7DF6E012 for ; Mon, 20 Oct 2014 05:35:54 -0700 (PDT) Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga101.jf.intel.com with ESMTP; 20 Oct 2014 05:35:35 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.04,756,1406617200"; d="scan'208";a="621838699" Received: from vkannan-desktop.iind.intel.com ([10.223.25.137]) by orsmga002.jf.intel.com with ESMTP; 20 Oct 2014 05:34:51 -0700 From: Vandana Kannan To: intel-gfx@lists.freedesktop.org Date: Mon, 20 Oct 2014 18:20:07 +0530 Message-Id: <1413809409-8569-6-git-send-email-vandana.kannan@intel.com> X-Mailer: git-send-email 2.0.1 In-Reply-To: <1413809409-8569-1-git-send-email-vandana.kannan@intel.com> References: <1413809409-8569-1-git-send-email-vandana.kannan@intel.com> Subject: [Intel-gfx] [RFC 5/7] drm/i915: Split PPS reg write func based on platform X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-5.6 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The difference between vlv and other platforms is w.r.t registers and port selection. Splitting the function to get value to be programmed based on platform and making the part which writes into registers common. Signed-off-by: Vandana Kannan --- drivers/gpu/drm/i915/i915_drv.h | 4 ++ drivers/gpu/drm/i915/intel_panel.c | 85 +++++++++++++++++++++++++------------- 2 files changed, 60 insertions(+), 29 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 1446d02..da0eede 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -511,6 +511,10 @@ struct drm_i915_display_funcs { struct edp_power_seq (*setup_panel_power_seq) (struct intel_connector *connector); + void (*set_pps_registers)(struct intel_connector *connector, + enum port port, int *pp_ctrl_reg, + int *pp_on_reg, int *pp_off_reg, + int *pp_div_reg, int *port_sel, int *div); }; struct intel_uncore_funcs { diff --git a/drivers/gpu/drm/i915/intel_panel.c b/drivers/gpu/drm/i915/intel_panel.c index 75172ab..c5e6c10 100644 --- a/drivers/gpu/drm/i915/intel_panel.c +++ b/drivers/gpu/drm/i915/intel_panel.c @@ -1346,32 +1346,67 @@ void intel_panel_init_backlight_funcs(struct drm_device *dev) } } -void -intel_panel_set_pps_registers(struct intel_connector *connector, - enum port port) +static void vlv_set_pps_registers(struct intel_connector *connector, + enum port port, int *pp_ctrl_reg, + int *pp_on_reg, int *pp_off_reg, + int *pp_div_reg, int *port_sel, int *div) { struct drm_device *dev = connector->base.dev; struct drm_i915_private *dev_priv = dev->dev_private; struct drm_encoder *encoder = connector->base.encoder; struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); - struct intel_panel *panel = &connector->panel; - u32 pp_on, pp_off, pp_div, port_sel = 0; - int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev); - int pp_on_reg, pp_off_reg, pp_div_reg; + enum pipe pipe = PIPE_A; + + pipe = vlv_power_sequencer_pipe(&intel_dig_port->dp); lockdep_assert_held(&dev_priv->pps_mutex); - if (HAS_PCH_SPLIT(dev)) { - pp_on_reg = PCH_PP_ON_DELAYS; - pp_off_reg = PCH_PP_OFF_DELAYS; - pp_div_reg = PCH_PP_DIVISOR; - } else { - enum pipe pipe = vlv_power_sequencer_pipe(&intel_dig_port->dp); + *pp_ctrl_reg = 0; + *pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe); + *pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe); + *pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe); + + *port_sel = PANEL_PORT_SELECT_VLV(port); + *div = intel_hrawclk(dev); +} - pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe); - pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe); - pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe); +static void pch_set_pps_registers(struct intel_connector *connector, + enum port port, int *pp_ctrl_reg, + int *pp_on_reg, int *pp_off_reg, + int *pp_div_reg, int *port_sel, int *div) +{ + struct drm_device *dev = connector->base.dev; + struct drm_i915_private *dev_priv = dev->dev_private; + + lockdep_assert_held(&dev_priv->pps_mutex); + + *pp_ctrl_reg = 0; + *pp_on_reg = PCH_PP_ON_DELAYS; + *pp_off_reg = PCH_PP_OFF_DELAYS; + *pp_div_reg = PCH_PP_DIVISOR; + + if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) { + if (port == PORT_A) + *port_sel = PANEL_PORT_SELECT_DPA; + else + *port_sel = PANEL_PORT_SELECT_DPD; } + *div = intel_pch_rawclk(dev); +} + +void +intel_panel_set_pps_registers(struct intel_connector *connector, + enum port port) +{ + struct drm_device *dev = connector->base.dev; + struct drm_i915_private *dev_priv = dev->dev_private; + struct intel_panel *panel = &connector->panel; + u32 pp_on, pp_off, pp_div, port_sel = 0, div; + int pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg; + + dev_priv->display.set_pps_registers(connector, port, &pp_ctrl_reg, + &pp_on_reg, &pp_off_reg, &pp_div_reg, + &port_sel, &div); /* * And finally store the new values in the power sequencer. The @@ -1393,17 +1428,6 @@ intel_panel_set_pps_registers(struct intel_connector *connector, pp_div |= (DIV_ROUND_UP(panel->pps.panel_power_cycle_delay, 1000) << PANEL_POWER_CYCLE_DELAY_SHIFT); - /* Haswell doesn't have any port selection bits for the panel - * power sequencer any more. */ - if (IS_VALLEYVIEW(dev)) { - port_sel = PANEL_PORT_SELECT_VLV(port); - } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) { - if (port == PORT_A) - port_sel = PANEL_PORT_SELECT_DPA; - else - port_sel = PANEL_PORT_SELECT_DPD; - } - pp_on |= port_sel; I915_WRITE(pp_on_reg, pp_on); @@ -1561,10 +1585,13 @@ void intel_panel_init_pps_funcs(struct drm_device *dev) { struct drm_i915_private *dev_priv = dev->dev_private; - if (IS_VALLEYVIEW(dev)) + if (IS_VALLEYVIEW(dev)) { dev_priv->display.setup_panel_power_seq = vlv_setup_pps; - else + dev_priv->display.set_pps_registers = vlv_set_pps_registers; + } else { dev_priv->display.setup_panel_power_seq = pch_setup_pps; + dev_priv->display.set_pps_registers = pch_set_pps_registers; + } }