From patchwork Thu Oct 23 18:50:44 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jesse Barnes X-Patchwork-Id: 5142691 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id AB7629F40A for ; Thu, 23 Oct 2014 18:51:21 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 7B12620222 for ; Thu, 23 Oct 2014 18:51:20 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 72811201FB for ; Thu, 23 Oct 2014 18:51:19 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 7F27A6E501; Thu, 23 Oct 2014 11:51:18 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-pa0-f44.google.com (mail-pa0-f44.google.com [209.85.220.44]) by gabe.freedesktop.org (Postfix) with ESMTP id E80396E500 for ; Thu, 23 Oct 2014 11:51:14 -0700 (PDT) Received: by mail-pa0-f44.google.com with SMTP id et14so1582993pad.31 for ; Thu, 23 Oct 2014 11:51:14 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=from:to:subject:date:message-id:in-reply-to:references; bh=QOCTJl9zWyT1lHEIer83nZ/O3YkALLGdwDaH75HPT9Q=; b=Ju86VvgGnXKp1xzG3cPaPkxSf8ZoWc6V1C1RyGddz9Nr9tGoCsdVz9gpQ6qAP2FVgf VMg0nkTGvfYk9R6VFj/bShbHyTFtnsXJcSqVo5hHus/+an6SOSNhD+suJP69rEvhtU8B zK/Ac2ma4/E2AIECpotjtFtqwKPfUkCmgAyX4JPAvv5S7ZnJWO3UGMenAK7NVval8UZM W9uA18+FPNMXdnQfpmjWe8Renu6BQ4p8/8+sbME/c6bsrcdD6/QF7+o5QYXf3TC1+LIH CitE/ZvEpfNhBMOSiBPFQ5ADTilgqH0hUS7fjf7udMeA8GwVWe+6s0pr3t8xHH/oZq5r jIWw== X-Received: by 10.68.221.33 with SMTP id qb1mr2947569pbc.167.1414090274685; Thu, 23 Oct 2014 11:51:14 -0700 (PDT) Received: from jbarnes-t420.intel.com (c-67-161-37-189.hsd1.ca.comcast.net. [67.161.37.189]) by mx.google.com with ESMTPSA id yk3sm2096713pbb.60.2014.10.23.11.51.13 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 23 Oct 2014 11:51:14 -0700 (PDT) From: Jesse Barnes To: intel-gfx@lists.freedesktop.org Date: Thu, 23 Oct 2014 11:50:44 -0700 Message-Id: <1414090247-28930-3-git-send-email-jbarnes@virtuousgeek.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1414090247-28930-1-git-send-email-jbarnes@virtuousgeek.org> References: <1414090247-28930-1-git-send-email-jbarnes@virtuousgeek.org> Subject: [Intel-gfx] [PATCH 3/6] drm/i915/hdmi: fetch infoframe status in get_config X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-5.6 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This is useful for checking things later. Signed-off-by: Jesse Barnes --- drivers/gpu/drm/i915/intel_drv.h | 4 +++ drivers/gpu/drm/i915/intel_hdmi.c | 61 +++++++++++++++++++++++++++++++++++++++ 2 files changed, 65 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index 5ab813c..cdace63 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -290,6 +290,9 @@ struct intel_crtc_config { * between pch encoders and cpu encoders. */ bool has_pch_encoder; + /* Are we sending infoframes on the attached port */ + bool has_infoframe; + /* CPU Transcoder for the pipe. Currently this can only differ from the * pipe on Haswell (where we have a special eDP transcoder). */ enum transcoder cpu_transcoder; @@ -541,6 +544,7 @@ struct intel_hdmi { void (*set_infoframes)(struct drm_encoder *encoder, bool enable, struct drm_display_mode *adjusted_mode); + bool (*infoframe_enabled)(struct drm_encoder *encoder); }; struct intel_dp_mst_encoder; diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c index 8b5f3aa..75efe4c 100644 --- a/drivers/gpu/drm/i915/intel_hdmi.c +++ b/drivers/gpu/drm/i915/intel_hdmi.c @@ -166,6 +166,15 @@ static void g4x_write_infoframe(struct drm_encoder *encoder, POSTING_READ(VIDEO_DIP_CTL); } +static bool g4x_infoframe_enabled(struct drm_encoder *encoder) +{ + struct drm_device *dev = encoder->dev; + struct drm_i915_private *dev_priv = dev->dev_private; + u32 val = I915_READ(VIDEO_DIP_CTL); + + return val & VIDEO_DIP_ENABLE; +} + static void ibx_write_infoframe(struct drm_encoder *encoder, enum hdmi_infoframe_type type, const void *frame, ssize_t len) @@ -204,6 +213,17 @@ static void ibx_write_infoframe(struct drm_encoder *encoder, POSTING_READ(reg); } +static bool ibx_infoframe_enabled(struct drm_encoder *encoder) +{ + struct drm_device *dev = encoder->dev; + struct drm_i915_private *dev_priv = dev->dev_private; + struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); + int reg = TVIDEO_DIP_CTL(intel_crtc->pipe); + u32 val = I915_READ(reg); + + return val & VIDEO_DIP_ENABLE; +} + static void cpt_write_infoframe(struct drm_encoder *encoder, enum hdmi_infoframe_type type, const void *frame, ssize_t len) @@ -245,6 +265,17 @@ static void cpt_write_infoframe(struct drm_encoder *encoder, POSTING_READ(reg); } +static bool cpt_infoframe_enabled(struct drm_encoder *encoder) +{ + struct drm_device *dev = encoder->dev; + struct drm_i915_private *dev_priv = dev->dev_private; + struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); + int reg = TVIDEO_DIP_CTL(intel_crtc->pipe); + u32 val = I915_READ(reg); + + return val & VIDEO_DIP_ENABLE; +} + static void vlv_write_infoframe(struct drm_encoder *encoder, enum hdmi_infoframe_type type, const void *frame, ssize_t len) @@ -283,6 +314,17 @@ static void vlv_write_infoframe(struct drm_encoder *encoder, POSTING_READ(reg); } +static bool vlv_infoframe_enabled(struct drm_encoder *encoder) +{ + struct drm_device *dev = encoder->dev; + struct drm_i915_private *dev_priv = dev->dev_private; + struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); + int reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe); + u32 val = I915_READ(reg); + + return val & VIDEO_DIP_ENABLE; +} + static void hsw_write_infoframe(struct drm_encoder *encoder, enum hdmi_infoframe_type type, const void *frame, ssize_t len) @@ -320,6 +362,17 @@ static void hsw_write_infoframe(struct drm_encoder *encoder, POSTING_READ(ctl_reg); } +static bool hsw_infoframe_enabled(struct drm_encoder *encoder) +{ + struct drm_device *dev = encoder->dev; + struct drm_i915_private *dev_priv = dev->dev_private; + struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); + u32 ctl_reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config.cpu_transcoder); + u32 val = I915_READ(ctl_reg); + + return val & VIDEO_DIP_ENABLE; +} + /* * The data we write to the DIP data buffer registers is 1 byte bigger than the * HDMI infoframe size because of an ECC/reserved byte at position 3 (starting @@ -732,6 +785,9 @@ static void intel_hdmi_get_config(struct intel_encoder *encoder, if (tmp & HDMI_MODE_SELECT_HDMI) pipe_config->has_hdmi_sink = true; + if (intel_hdmi->infoframe_enabled(&encoder->base)) + pipe_config->has_infoframe = true; + if (tmp & SDVO_AUDIO_ENABLE) pipe_config->has_audio = true; @@ -1616,18 +1672,23 @@ void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port, if (IS_VALLEYVIEW(dev)) { intel_hdmi->write_infoframe = vlv_write_infoframe; intel_hdmi->set_infoframes = vlv_set_infoframes; + intel_hdmi->infoframe_enabled = vlv_infoframe_enabled; } else if (IS_G4X(dev)) { intel_hdmi->write_infoframe = g4x_write_infoframe; intel_hdmi->set_infoframes = g4x_set_infoframes; + intel_hdmi->infoframe_enabled = g4x_infoframe_enabled; } else if (HAS_DDI(dev)) { intel_hdmi->write_infoframe = hsw_write_infoframe; intel_hdmi->set_infoframes = hsw_set_infoframes; + intel_hdmi->infoframe_enabled = hsw_infoframe_enabled; } else if (HAS_PCH_IBX(dev)) { intel_hdmi->write_infoframe = ibx_write_infoframe; intel_hdmi->set_infoframes = ibx_set_infoframes; + intel_hdmi->infoframe_enabled = ibx_infoframe_enabled; } else { intel_hdmi->write_infoframe = cpt_write_infoframe; intel_hdmi->set_infoframes = cpt_set_infoframes; + intel_hdmi->infoframe_enabled = cpt_infoframe_enabled; } if (HAS_DDI(dev))