From patchwork Sat Oct 25 11:51:53 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: akash.goel@intel.com X-Patchwork-Id: 5151181 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id DC42A9F30B for ; Sat, 25 Oct 2014 11:47:05 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id BA42920204 for ; Sat, 25 Oct 2014 11:47:04 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 5B283201E4 for ; Sat, 25 Oct 2014 11:47:03 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id BCE2B6E696; Sat, 25 Oct 2014 04:47:02 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTP id 3AEF86E696 for ; Sat, 25 Oct 2014 04:47:01 -0700 (PDT) Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga102.jf.intel.com with ESMTP; 25 Oct 2014 04:45:47 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.04,786,1406617200"; d="scan'208";a="625184016" Received: from akashgoe-desktop.iind.intel.com ([10.223.82.144]) by orsmga002.jf.intel.com with ESMTP; 25 Oct 2014 04:46:59 -0700 From: akash.goel@intel.com To: intel-gfx@lists.freedesktop.org Date: Sat, 25 Oct 2014 17:21:53 +0530 Message-Id: <1414237913-7809-1-git-send-email-akash.goel@intel.com> X-Mailer: git-send-email 1.9.2 In-Reply-To: <1414083347-31259-1-git-send-email-chris@chris-wilson.co.uk> References: <1414083347-31259-1-git-send-email-chris@chris-wilson.co.uk> Cc: Akash Goel Subject: [Intel-gfx] [PATCH] intel: New libdrm interface to create unbound wc user mappings for objects X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-5.7 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Akash Goel A new libdrm interface 'drm_intel_gem_bo_map_wc' is provided by this patch. Through this interface Gfx clients can create write combining virtual mappings of the Gem object. It will provide the same funtionality of 'mmap_gtt' interface without the constraints of limited aperture space, but provided clients handles the linear to tile conversion on their own. This patch is intended for improving the CPU write operation performance, as with such mapping, writes are almost 50% faster than with mmap_gtt. Also it avoids the Cache flush after update from CPU side, when object is passed on to GPU, which will be the case if regular mmap interface is used. This type of mapping is specially useful in case of sub-region update, i.e. when only a portion of the object is to be updated. Also there is a support for the unsynchronized version of this interface named 'drm_intel_gem_bo_map_wc_unsynchronized', through which wc virtual mappings, but unsynchronized one, can be created of the Gem object. To ensure the cache coherency, before using this mapping, the GTT domain has been reused here. This provides the required Cache flush if the object is in CPU domain or synchronization against the concurrent rendering The drm_i915_gem_mmap structure (for the DRM_I915_GEM_MMAP_IOCTL) has been extended with a new flags field (defaulting to 0 for existent users). In order for userspace to detect the extended ioctl, a new parameter I915_PARAM_HAS_EXT_MMAP has been added for versioning the ioctl interface. v2: Aligned with the v2 of the corresponding kernel patch (Chris) Signed-off-by: Akash Goel Signed-off-by: Chris Wilson --- include/drm/i915_drm.h | 9 ++++ intel/intel_bufmgr.h | 3 ++ intel/intel_bufmgr_gem.c | 124 +++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 136 insertions(+) diff --git a/include/drm/i915_drm.h b/include/drm/i915_drm.h index 15dd01d..a91a1d0 100644 --- a/include/drm/i915_drm.h +++ b/include/drm/i915_drm.h @@ -340,6 +340,7 @@ typedef struct drm_i915_irq_wait { #define I915_PARAM_HAS_EXEC_HANDLE_LUT 26 #define I915_PARAM_HAS_WT 27 #define I915_PARAM_CMD_PARSER_VERSION 28 +#define I915_PARAM_MMAP_VERSION 29 typedef struct drm_i915_getparam { int param; @@ -487,6 +488,14 @@ struct drm_i915_gem_mmap { * This is a fixed-size type for 32/64 compatibility. */ __u64 addr_ptr; + + /** + * Flags for extended behaviour. + * + * Added in version 2. + */ + __u64 flags; +#define I915_MMAP_WC 0x1 }; struct drm_i915_gem_mmap_gtt { diff --git a/intel/intel_bufmgr.h b/intel/intel_bufmgr.h index be83a56..bda4115 100644 --- a/intel/intel_bufmgr.h +++ b/intel/intel_bufmgr.h @@ -177,6 +177,9 @@ void drm_intel_bufmgr_gem_set_vma_cache_size(drm_intel_bufmgr *bufmgr, int drm_intel_gem_bo_map_unsynchronized(drm_intel_bo *bo); int drm_intel_gem_bo_map_gtt(drm_intel_bo *bo); int drm_intel_gem_bo_unmap_gtt(drm_intel_bo *bo); +int drm_intel_gem_bo_map_wc_unsynchronized(drm_intel_bo *bo); +int drm_intel_gem_bo_map_wc(drm_intel_bo *bo); +int drm_intel_gem_bo_unmap_wc(drm_intel_bo *bo); int drm_intel_gem_bo_get_reloc_count(drm_intel_bo *bo); void drm_intel_gem_bo_clear_relocs(drm_intel_bo *bo, int start); diff --git a/intel/intel_bufmgr_gem.c b/intel/intel_bufmgr_gem.c index f2f4fea..95c588f 100644 --- a/intel/intel_bufmgr_gem.c +++ b/intel/intel_bufmgr_gem.c @@ -184,6 +184,8 @@ struct _drm_intel_bo_gem { int reloc_count; /** Mapped address for the buffer, saved across map/unmap cycles */ void *mem_virtual; + /** Uncached Mapped address for the buffer, saved across map/unmap cycles */ + void *mem_wc_virtual; /** GTT virtual address for the buffer, saved across map/unmap cycles */ void *gtt_virtual; /** @@ -1267,6 +1269,121 @@ static void drm_intel_gem_bo_unreference(drm_intel_bo *bo) } } +static int +map_wc(drm_intel_bo *bo) +{ + drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr; + drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo; + int ret; + + if (bo_gem->is_userptr) + return -EINVAL; + + if (bo_gem->map_count++ == 0) + drm_intel_gem_bo_open_vma(bufmgr_gem, bo_gem); + + /* Get a mapping of the buffer if we haven't before. */ + if (bo_gem->mem_wc_virtual == NULL) { + struct drm_i915_gem_mmap mmap_arg; + + DBG("bo_map_wc: mmap %d (%s), map_count=%d\n", + bo_gem->gem_handle, bo_gem->name, bo_gem->map_count); + + VG_CLEAR(mmap_arg); + mmap_arg.handle = bo_gem->gem_handle; + /* To indicate the uncached virtual mapping to KMD */ + mmap_arg.flags = I915_MMAP_WC; + mmap_arg.offset = 0; + mmap_arg.size = bo->size; + ret = drmIoctl(bufmgr_gem->fd, + DRM_IOCTL_I915_GEM_MMAP, + &mmap_arg); + if (ret != 0) { + ret = -errno; + DBG("%s:%d: Error mapping buffer %d (%s): %s .\n", + __FILE__, __LINE__, bo_gem->gem_handle, + bo_gem->name, strerror(errno)); + if (--bo_gem->map_count == 0) + drm_intel_gem_bo_close_vma(bufmgr_gem, bo_gem); + pthread_mutex_unlock(&bufmgr_gem->lock); + return ret; + } + VG(VALGRIND_MALLOCLIKE_BLOCK(mmap_arg.addr_ptr, mmap_arg.size, 0, 1)); + bo_gem->mem_wc_virtual = (void *)(uintptr_t) mmap_arg.addr_ptr; + } + + bo->virtual = bo_gem->mem_wc_virtual; + + DBG("bo_map_wc: %d (%s) -> %p\n", bo_gem->gem_handle, bo_gem->name, + bo_gem->mem_wc_virtual); + + return 0; +} + +/* To be used in a similar way to mmap_gtt */ +drm_public int +drm_intel_gem_bo_map_wc(drm_intel_bo *bo) { + drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr; + drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo; + struct drm_i915_gem_set_domain set_domain; + int ret; + + pthread_mutex_lock(&bufmgr_gem->lock); + + ret = map_wc(bo); + if (ret) { + pthread_mutex_unlock(&bufmgr_gem->lock); + return ret; + } + + /* Now move it to the GTT domain so that the GPU and CPU + * caches are flushed and the GPU isn't actively using the + * buffer. + * + * The domain change is done even for the objects which + * are not bounded. For them first the pages are acquired, + * before the domain change. + */ + VG_CLEAR(set_domain); + set_domain.handle = bo_gem->gem_handle; + set_domain.read_domains = I915_GEM_DOMAIN_GTT; + set_domain.write_domain = I915_GEM_DOMAIN_GTT; + ret = drmIoctl(bufmgr_gem->fd, + DRM_IOCTL_I915_GEM_SET_DOMAIN, + &set_domain); + if (ret != 0) { + DBG("%s:%d: Error setting domain %d: %s\n", + __FILE__, __LINE__, bo_gem->gem_handle, + strerror(errno)); + } + drm_intel_gem_bo_mark_mmaps_incoherent(bo); + VG(VALGRIND_MAKE_MEM_DEFINED(bo_gem->mem_virtual, bo->size)); + pthread_mutex_unlock(&bufmgr_gem->lock); + + return 0; +} + +drm_public int +drm_intel_gem_bo_map_wc_unsynchronized(drm_intel_bo *bo) { + drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr; +#ifdef HAVE_VALGRIND + drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo; +#endif + int ret; + + pthread_mutex_lock(&bufmgr_gem->lock); + + ret = map_wc(bo); + if (ret == 0) { + drm_intel_gem_bo_mark_mmaps_incoherent(bo); + VG(VALGRIND_MAKE_MEM_DEFINED(bo_gem->gtt_virtual, bo->size)); + } + + pthread_mutex_unlock(&bufmgr_gem->lock); + + return ret; +} + static int drm_intel_gem_bo_map(drm_intel_bo *bo, int write_enable) { drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr; @@ -1293,6 +1410,7 @@ static int drm_intel_gem_bo_map(drm_intel_bo *bo, int write_enable) VG_CLEAR(mmap_arg); mmap_arg.handle = bo_gem->gem_handle; + mmap_arg.flags = 0; mmap_arg.offset = 0; mmap_arg.size = bo->size; ret = drmIoctl(bufmgr_gem->fd, @@ -1553,6 +1671,12 @@ static int drm_intel_gem_bo_unmap(drm_intel_bo *bo) } drm_public int +drm_intel_gem_bo_unmap_wc(drm_intel_bo *bo) +{ + return drm_intel_gem_bo_unmap(bo); +} + +drm_public int drm_intel_gem_bo_unmap_gtt(drm_intel_bo *bo) { return drm_intel_gem_bo_unmap(bo);