drm/i915: don't try using training pattern 3 on pre-haswell

Commit Message

Dave Airlie Oct. 29, 2014, 7:02 a.m. UTC

From: Dave Airlie <[e-mail]>

Ivybridge + 30" monitor prints a drm error on every modeset, since
IVB doesn't support DP3 we should even bother trying to use it.

Reviewed-by: Daniel Vetter <[e-mail]> (on irc)
Signed-off-by: Dave Airlie <[e-mail]>
---
 drivers/gpu/drm/i915/intel_dp.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

Comments

Daniel Vetter Oct. 29, 2014, 7:40 a.m. UTC | #1

On Wed, Oct 29, 2014 at 05:02:50PM +1000, Dave Airlie wrote:
> From: Dave Airlie <[e-mail]>
> 
> Ivybridge + 30" monitor prints a drm error on every modeset, since
> IVB doesn't support DP3 we should even bother trying to use it.
> 
> Reviewed-by: Daniel Vetter <[e-mail]> (on irc)
> Signed-off-by: Dave Airlie <[e-mail]>

This regression has been introduced in

commit 06ea66b6bb445043dc25a9626254d5c130093199
Author: Todd Previte <[e-mail]>
Date:   Mon Jan 20 10:19:39 2014 -0700

    drm/i915: Enable 5.4Ghz (HBR2) link rate for Displayport 1.2-capable devices

Cc: Todd Previte <[e-mail]>
Cc: [e-mail]

Jani, can you please pick this one up?
-Daniel

> ---
>  drivers/gpu/drm/i915/intel_dp.c | 4 +++-
>  1 file changed, 3 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index f6a3fdd..87cfb92 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -3547,13 +3547,15 @@ intel_dp_start_link_train(struct intel_dp *intel_dp)
>  void
>  intel_dp_complete_link_train(struct intel_dp *intel_dp)
>  {
> +	struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
> +	struct drm_device *dev = encoder->dev;
>  	bool channel_eq = false;
>  	int tries, cr_tries;
>  	uint32_t DP = intel_dp->DP;
>  	uint32_t training_pattern = DP_TRAINING_PATTERN_2;
>  
>  	/* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/
> -	if (intel_dp->link_bw == DP_LINK_BW_5_4 || intel_dp->use_tps3)
> +	if ((intel_dp->link_bw == DP_LINK_BW_5_4 || intel_dp->use_tps3) && !HAS_DDI(dev))
>  		training_pattern = DP_TRAINING_PATTERN_3;
>  
>  	/* channel equalization */
> -- 
> 1.9.3
> 
> _______________________________________________
> Intel-gfx mailing list
> [e-mail]
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Ville Syrjala Oct. 29, 2014, 8:15 a.m. UTC | #2

On Wed, Oct 29, 2014 at 05:02:50PM +1000, Dave Airlie wrote:
> From: Dave Airlie <[e-mail]>
> 
> Ivybridge + 30" monitor prints a drm error on every modeset, since
> IVB doesn't support DP3 we should even bother trying to use it.
> 
> Reviewed-by: Daniel Vetter <[e-mail]> (on irc)
> Signed-off-by: Dave Airlie <[e-mail]>
> ---
>  drivers/gpu/drm/i915/intel_dp.c | 4 +++-
>  1 file changed, 3 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index f6a3fdd..87cfb92 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -3547,13 +3547,15 @@ intel_dp_start_link_train(struct intel_dp *intel_dp)
>  void
>  intel_dp_complete_link_train(struct intel_dp *intel_dp)
>  {
> +	struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
> +	struct drm_device *dev = encoder->dev;
>  	bool channel_eq = false;
>  	int tries, cr_tries;
>  	uint32_t DP = intel_dp->DP;
>  	uint32_t training_pattern = DP_TRAINING_PATTERN_2;
>  
>  	/* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/
> -	if (intel_dp->link_bw == DP_LINK_BW_5_4 || intel_dp->use_tps3)
> +	if ((intel_dp->link_bw == DP_LINK_BW_5_4 || intel_dp->use_tps3) && !HAS_DDI(dev))

CHV has pattern 3.

>  		training_pattern = DP_TRAINING_PATTERN_3;
>  
>  	/* channel equalization */
> -- 
> 1.9.3
> 
> _______________________________________________
> Intel-gfx mailing list
> [e-mail]
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Ville Syrjala Oct. 29, 2014, 8:22 a.m. UTC | #3

On Wed, Oct 29, 2014 at 10:15:01AM +0200, Ville Syrjälä wrote:
> On Wed, Oct 29, 2014 at 05:02:50PM +1000, Dave Airlie wrote:
> > From: Dave Airlie <[e-mail]>
> > 
> > Ivybridge + 30" monitor prints a drm error on every modeset, since
> > IVB doesn't support DP3 we should even bother trying to use it.
> > 
> > Reviewed-by: Daniel Vetter <[e-mail]> (on irc)
> > Signed-off-by: Dave Airlie <[e-mail]>
> > ---
> >  drivers/gpu/drm/i915/intel_dp.c | 4 +++-
> >  1 file changed, 3 insertions(+), 1 deletion(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> > index f6a3fdd..87cfb92 100644
> > --- a/drivers/gpu/drm/i915/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > @@ -3547,13 +3547,15 @@ intel_dp_start_link_train(struct intel_dp *intel_dp)
> >  void
> >  intel_dp_complete_link_train(struct intel_dp *intel_dp)
> >  {
> > +	struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
> > +	struct drm_device *dev = encoder->dev;
> >  	bool channel_eq = false;
> >  	int tries, cr_tries;
> >  	uint32_t DP = intel_dp->DP;
> >  	uint32_t training_pattern = DP_TRAINING_PATTERN_2;
> >  
> >  	/* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/
> > -	if (intel_dp->link_bw == DP_LINK_BW_5_4 || intel_dp->use_tps3)
> > +	if ((intel_dp->link_bw == DP_LINK_BW_5_4 || intel_dp->use_tps3) && !HAS_DDI(dev))
> 
> CHV has pattern 3.

Also what's that '!' doing there?

> 
> >  		training_pattern = DP_TRAINING_PATTERN_3;
> >  
> >  	/* channel equalization */
> > -- 
> > 1.9.3
> > 
> > _______________________________________________
> > Intel-gfx mailing list
> > [e-mail]
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> -- 
> Ville Syrjälä
> Intel OTC
> _______________________________________________
> Intel-gfx mailing list
> [e-mail]
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Jani Nikula Oct. 29, 2014, 8:23 a.m. UTC | #4

On Wed, 29 Oct 2014, Ville Syrjälä <[e-mail]> wrote:
> On Wed, Oct 29, 2014 at 05:02:50PM +1000, Dave Airlie wrote:
>> From: Dave Airlie <[e-mail]>
>> 
>> Ivybridge + 30" monitor prints a drm error on every modeset, since
>> IVB doesn't support DP3 we should even bother trying to use it.
>> 
>> Reviewed-by: Daniel Vetter <[e-mail]> (on irc)
>> Signed-off-by: Dave Airlie <[e-mail]>
>> ---
>>  drivers/gpu/drm/i915/intel_dp.c | 4 +++-
>>  1 file changed, 3 insertions(+), 1 deletion(-)
>> 
>> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
>> index f6a3fdd..87cfb92 100644
>> --- a/drivers/gpu/drm/i915/intel_dp.c
>> +++ b/drivers/gpu/drm/i915/intel_dp.c
>> @@ -3547,13 +3547,15 @@ intel_dp_start_link_train(struct intel_dp *intel_dp)
>>  void
>>  intel_dp_complete_link_train(struct intel_dp *intel_dp)
>>  {
>> +	struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
>> +	struct drm_device *dev = encoder->dev;
>>  	bool channel_eq = false;
>>  	int tries, cr_tries;
>>  	uint32_t DP = intel_dp->DP;
>>  	uint32_t training_pattern = DP_TRAINING_PATTERN_2;
>>  
>>  	/* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/
>> -	if (intel_dp->link_bw == DP_LINK_BW_5_4 || intel_dp->use_tps3)
>> +	if ((intel_dp->link_bw == DP_LINK_BW_5_4 || intel_dp->use_tps3) && !HAS_DDI(dev))
>
> CHV has pattern 3.

Is "supports tps3" the same set of platforms as "supports 5.4 Gbps"? We
should abstract the check from intel_dp_max_link_bw.

Jani.


>
>>  		training_pattern = DP_TRAINING_PATTERN_3;
>>  
>>  	/* channel equalization */
>> -- 
>> 1.9.3
>> 
>> _______________________________________________
>> Intel-gfx mailing list
>> [e-mail]
>> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
> -- 
> Ville Syrjälä
> Intel OTC
> _______________________________________________
> dri-devel mailing list
> [e-mail]
> http://lists.freedesktop.org/mailman/listinfo/dri-devel

Ville Syrjala Oct. 29, 2014, 8:40 a.m. UTC | #5

On Wed, Oct 29, 2014 at 10:23:50AM +0200, Jani Nikula wrote:
> On Wed, 29 Oct 2014, Ville Syrjälä <[e-mail]> wrote:
> > On Wed, Oct 29, 2014 at 05:02:50PM +1000, Dave Airlie wrote:
> >> From: Dave Airlie <[e-mail]>
> >> 
> >> Ivybridge + 30" monitor prints a drm error on every modeset, since
> >> IVB doesn't support DP3 we should even bother trying to use it.
> >> 
> >> Reviewed-by: Daniel Vetter <[e-mail]> (on irc)
> >> Signed-off-by: Dave Airlie <[e-mail]>
> >> ---
> >>  drivers/gpu/drm/i915/intel_dp.c | 4 +++-
> >>  1 file changed, 3 insertions(+), 1 deletion(-)
> >> 
> >> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> >> index f6a3fdd..87cfb92 100644
> >> --- a/drivers/gpu/drm/i915/intel_dp.c
> >> +++ b/drivers/gpu/drm/i915/intel_dp.c
> >> @@ -3547,13 +3547,15 @@ intel_dp_start_link_train(struct intel_dp *intel_dp)
> >>  void
> >>  intel_dp_complete_link_train(struct intel_dp *intel_dp)
> >>  {
> >> +	struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
> >> +	struct drm_device *dev = encoder->dev;
> >>  	bool channel_eq = false;
> >>  	int tries, cr_tries;
> >>  	uint32_t DP = intel_dp->DP;
> >>  	uint32_t training_pattern = DP_TRAINING_PATTERN_2;
> >>  
> >>  	/* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/
> >> -	if (intel_dp->link_bw == DP_LINK_BW_5_4 || intel_dp->use_tps3)
> >> +	if ((intel_dp->link_bw == DP_LINK_BW_5_4 || intel_dp->use_tps3) && !HAS_DDI(dev))
> >
> > CHV has pattern 3.
> 
> Is "supports tps3" the same set of platforms as "supports 5.4 Gbps"? We
> should abstract the check from intel_dp_max_link_bw.

Not quite. HSW-ULX supports pattern 3 even though it doesn't do 5.4 Gbps.

> 
> Jani.
> 
> 
> >
> >>  		training_pattern = DP_TRAINING_PATTERN_3;
> >>  
> >>  	/* channel equalization */
> >> -- 
> >> 1.9.3
> >> 
> >> _______________________________________________
> >> Intel-gfx mailing list
> >> [e-mail]
> >> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> >
> > -- 
> > Ville Syrjälä
> > Intel OTC
> > _______________________________________________
> > dri-devel mailing list
> > [e-mail]
> > http://lists.freedesktop.org/mailman/listinfo/dri-devel
> 
> -- 
> Jani Nikula, Intel Open Source Technology Center

Jani Nikula Oct. 29, 2014, 9:07 a.m. UTC | #6

On Wed, 29 Oct 2014, Ville Syrjälä <[e-mail]> wrote:
> On Wed, Oct 29, 2014 at 10:23:50AM +0200, Jani Nikula wrote:
>> On Wed, 29 Oct 2014, Ville Syrjälä <[e-mail]> wrote:
>> > On Wed, Oct 29, 2014 at 05:02:50PM +1000, Dave Airlie wrote:
>> >> From: Dave Airlie <[e-mail]>
>> >> 
>> >> Ivybridge + 30" monitor prints a drm error on every modeset, since
>> >> IVB doesn't support DP3 we should even bother trying to use it.
>> >> 
>> >> Reviewed-by: Daniel Vetter <[e-mail]> (on irc)
>> >> Signed-off-by: Dave Airlie <[e-mail]>
>> >> ---
>> >>  drivers/gpu/drm/i915/intel_dp.c | 4 +++-
>> >>  1 file changed, 3 insertions(+), 1 deletion(-)
>> >> 
>> >> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
>> >> index f6a3fdd..87cfb92 100644
>> >> --- a/drivers/gpu/drm/i915/intel_dp.c
>> >> +++ b/drivers/gpu/drm/i915/intel_dp.c
>> >> @@ -3547,13 +3547,15 @@ intel_dp_start_link_train(struct intel_dp *intel_dp)
>> >>  void
>> >>  intel_dp_complete_link_train(struct intel_dp *intel_dp)
>> >>  {
>> >> +	struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
>> >> +	struct drm_device *dev = encoder->dev;
>> >>  	bool channel_eq = false;
>> >>  	int tries, cr_tries;
>> >>  	uint32_t DP = intel_dp->DP;
>> >>  	uint32_t training_pattern = DP_TRAINING_PATTERN_2;
>> >>  
>> >>  	/* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/
>> >> -	if (intel_dp->link_bw == DP_LINK_BW_5_4 || intel_dp->use_tps3)
>> >> +	if ((intel_dp->link_bw == DP_LINK_BW_5_4 || intel_dp->use_tps3) && !HAS_DDI(dev))
>> >
>> > CHV has pattern 3.
>> 
>> Is "supports tps3" the same set of platforms as "supports 5.4 Gbps"? We
>> should abstract the check from intel_dp_max_link_bw.
>
> Not quite. HSW-ULX supports pattern 3 even though it doesn't do 5.4 Gbps.

How about [1] instead? I forgot --in-reply-to, sorry.

BR,
Jani.


[1] http://mid.gmane.org/[e-mail]

Jesse Barnes Oct. 30, 2014, 9:16 p.m. UTC | #7

On Wed, 29 Oct 2014 11:07:32 +0200
Jani Nikula <[e-mail]> wrote:

> On Wed, 29 Oct 2014, Ville Syrjälä <[e-mail]> wrote:
> > On Wed, Oct 29, 2014 at 10:23:50AM +0200, Jani Nikula wrote:
> >> On Wed, 29 Oct 2014, Ville Syrjälä <[e-mail]> wrote:
> >> > On Wed, Oct 29, 2014 at 05:02:50PM +1000, Dave Airlie wrote:
> >> >> From: Dave Airlie <[e-mail]>
> >> >> 
> >> >> Ivybridge + 30" monitor prints a drm error on every modeset, since
> >> >> IVB doesn't support DP3 we should even bother trying to use it.
> >> >> 
> >> >> Reviewed-by: Daniel Vetter <[e-mail]> (on irc)
> >> >> Signed-off-by: Dave Airlie <[e-mail]>
> >> >> ---
> >> >>  drivers/gpu/drm/i915/intel_dp.c | 4 +++-
> >> >>  1 file changed, 3 insertions(+), 1 deletion(-)
> >> >> 
> >> >> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> >> >> index f6a3fdd..87cfb92 100644
> >> >> --- a/drivers/gpu/drm/i915/intel_dp.c
> >> >> +++ b/drivers/gpu/drm/i915/intel_dp.c
> >> >> @@ -3547,13 +3547,15 @@ intel_dp_start_link_train(struct intel_dp *intel_dp)
> >> >>  void
> >> >>  intel_dp_complete_link_train(struct intel_dp *intel_dp)
> >> >>  {
> >> >> +	struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
> >> >> +	struct drm_device *dev = encoder->dev;
> >> >>  	bool channel_eq = false;
> >> >>  	int tries, cr_tries;
> >> >>  	uint32_t DP = intel_dp->DP;
> >> >>  	uint32_t training_pattern = DP_TRAINING_PATTERN_2;
> >> >>  
> >> >>  	/* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/
> >> >> -	if (intel_dp->link_bw == DP_LINK_BW_5_4 || intel_dp->use_tps3)
> >> >> +	if ((intel_dp->link_bw == DP_LINK_BW_5_4 || intel_dp->use_tps3) && !HAS_DDI(dev))
> >> >
> >> > CHV has pattern 3.
> >> 
> >> Is "supports tps3" the same set of platforms as "supports 5.4 Gbps"? We
> >> should abstract the check from intel_dp_max_link_bw.
> >
> > Not quite. HSW-ULX supports pattern 3 even though it doesn't do 5.4 Gbps.
> 
> How about [1] instead? I forgot --in-reply-to, sorry.
> 
> BR,
> Jani.
> 
> 
> [1] http://mid.gmane.org/[e-mail]

Looks like we need something like that at least, assuming we're not
hitting the link_bw == DP_LINK_BW_5_4 case.

Patch

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index f6a3fdd..87cfb92 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -3547,13 +3547,15 @@  intel_dp_start_link_train(struct intel_dp *intel_dp)
 void
 intel_dp_complete_link_train(struct intel_dp *intel_dp)
 {
+	struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
+	struct drm_device *dev = encoder->dev;
 	bool channel_eq = false;
 	int tries, cr_tries;
 	uint32_t DP = intel_dp->DP;
 	uint32_t training_pattern = DP_TRAINING_PATTERN_2;
 
 	/* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/
-	if (intel_dp->link_bw == DP_LINK_BW_5_4 || intel_dp->use_tps3)
+	if ((intel_dp->link_bw == DP_LINK_BW_5_4 || intel_dp->use_tps3) && !HAS_DDI(dev))
 		training_pattern = DP_TRAINING_PATTERN_3;
 
 	/* channel equalization */