From patchwork Wed Oct 29 09:32:35 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ander Conselvan de Oliveira X-Patchwork-Id: 5185961 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id BF2FAC11AC for ; Wed, 29 Oct 2014 09:33:36 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 0A25E20219 for ; Wed, 29 Oct 2014 09:33:36 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 2AD27201FA for ; Wed, 29 Oct 2014 09:33:35 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id B17256E4EE; Wed, 29 Oct 2014 02:33:34 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTP id 0FAF86E4EF for ; Wed, 29 Oct 2014 02:33:32 -0700 (PDT) Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by fmsmga102.fm.intel.com with ESMTP; 29 Oct 2014 02:33:26 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="4.97,862,1389772800"; d="scan'208";a="407739904" Received: from linux.jf.intel.com (HELO linux.intel.com) ([10.23.219.25]) by FMSMGA003.fm.intel.com with ESMTP; 29 Oct 2014 02:25:21 -0700 Received: from localhost (ander-mobl1.fi.intel.com [10.237.72.170]) by linux.intel.com (Postfix) with ESMTP id BA43D6A4083; Wed, 29 Oct 2014 02:32:34 -0700 (PDT) From: Ander Conselvan de Oliveira To: intel-gfx@lists.freedesktop.org Date: Wed, 29 Oct 2014 11:32:35 +0200 Message-Id: <1414575158-28148-7-git-send-email-ander.conselvan.de.oliveira@intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1414575158-28148-1-git-send-email-ander.conselvan.de.oliveira@intel.com> References: <1414575158-28148-1-git-send-email-ander.conselvan.de.oliveira@intel.com> Cc: Ander Conselvan de Oliveira , ville.syrjala@intel.com, shuang.he@linux.intel.com Subject: [Intel-gfx] [PATCH 6/9] drm/i915: Covert ILK-IVB to choose DPLLS before disabling CRTCs X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.8 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Use the infrastructure added in a previous patch to choose shared DPLLs and calculate clocks before touching the hardware. v2: Don't set mode_set hooks since dev_priv is kzalloc()'d (Ville) Signed-off-by: Ander Conselvan de Oliveira --- drivers/gpu/drm/i915/intel_display.c | 13 ++++--------- 1 file changed, 4 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index b946070..3e070d1 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -7408,9 +7408,7 @@ static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc, return dpll | DPLL_VCO_ENABLE; } -static int ironlake_crtc_mode_set(struct intel_crtc *crtc, - int x, int y, - struct drm_framebuffer *fb) +static int ironlake_crtc_compute_clock(struct intel_crtc *crtc) { struct drm_device *dev = crtc->base.dev; intel_clock_t clock, reduced_clock; @@ -7456,17 +7454,13 @@ static int ironlake_crtc_mode_set(struct intel_crtc *crtc, else crtc->new_config->dpll_hw_state.fp1 = fp; - if (intel_crtc_to_shared_dpll(crtc)) - intel_put_shared_dpll(crtc); - pll = intel_get_shared_dpll(crtc); if (pll == NULL) { DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n", pipe_name(crtc->pipe)); return -EINVAL; } - } else - intel_put_shared_dpll(crtc); + } if (is_lvds && has_reduced_clock && i915.powersave) crtc->lowfreq_avail = true; @@ -12470,7 +12464,8 @@ static void intel_init_display(struct drm_device *dev) } else if (HAS_PCH_SPLIT(dev)) { dev_priv->display.get_pipe_config = ironlake_get_pipe_config; dev_priv->display.get_plane_config = ironlake_get_plane_config; - dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set; + dev_priv->display.crtc_compute_clock = + ironlake_crtc_compute_clock; dev_priv->display.crtc_enable = ironlake_crtc_enable; dev_priv->display.crtc_disable = ironlake_crtc_disable; dev_priv->display.off = ironlake_crtc_off;