From patchwork Mon Nov 3 14:26:35 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Lespiau, Damien" X-Patchwork-Id: 5216921 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id B95EAC11AC for ; Mon, 3 Nov 2014 14:26:42 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id C88A02010F for ; Mon, 3 Nov 2014 14:26:41 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 90D6E200DE for ; Mon, 3 Nov 2014 14:26:40 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id A3EF16E023; Mon, 3 Nov 2014 06:26:39 -0800 (PST) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTP id 5BFBF6E023 for ; Mon, 3 Nov 2014 06:26:38 -0800 (PST) Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga103.jf.intel.com with ESMTP; 03 Nov 2014 06:24:40 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.07,308,1413270000"; d="scan'208";a="630335518" Received: from solender-mobl1.ger.corp.intel.com (HELO strange.ger.corp.intel.com) ([10.252.10.60]) by orsmga002.jf.intel.com with ESMTP; 03 Nov 2014 06:26:36 -0800 From: Damien Lespiau To: intel-gfx@lists.freedesktop.org Date: Mon, 3 Nov 2014 14:26:35 +0000 Message-Id: <1415024795-9894-1-git-send-email-damien.lespiau@intel.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <20141029165334.GB10649@intel.com> References: <20141029165334.GB10649@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 1/8 v2] drm/i915/skl: Make 'end' of the DDB allocation entry exclusive X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.8 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Ville suggested that we should use the same semantics as C arrays to reduce the number of those pesky +1/-1 in the allocation code. This patch leaves the debugfs file as is, showing the internal DDB allocation structure, not the values written in the registers. v2: Remove the test on ->end in skl_ddb_entry_size() (Ville) Reviewed-by: Ville Syrjälä Suggested-by: Ville Syrjälä Signed-off-by: Damien Lespiau --- drivers/gpu/drm/i915/i915_drv.h | 8 ++------ drivers/gpu/drm/i915/intel_pm.c | 28 +++++++++++++++++++--------- 2 files changed, 21 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 9b4e713..3b914d0 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1386,16 +1386,12 @@ struct ilk_wm_values { }; struct skl_ddb_entry { - uint16_t start, end; /* in number of blocks */ + uint16_t start, end; /* in number of blocks, 'end' is exclusive */ }; static inline uint16_t skl_ddb_entry_size(const struct skl_ddb_entry *entry) { - /* end not set, clearly no allocation here. start can be 0 though */ - if (entry->end == 0) - return 0; - - return entry->end - entry->start + 1; + return entry->end - entry->start; } static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1, diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 159c2e0..e417a6a 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -3040,7 +3040,7 @@ skl_ddb_get_pipe_allocation_limits(struct drm_device *dev, pipe_size = ddb_size / config->num_pipes_active; alloc->start = nth_active_pipe * ddb_size / config->num_pipes_active; - alloc->end = alloc->start + pipe_size - 1; + alloc->end = alloc->start + pipe_size; } static unsigned int skl_cursor_allocation(const struct intel_wm_config *config) @@ -3055,6 +3055,8 @@ static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry *entry, u32 reg) { entry->start = reg & 0x3ff; entry->end = (reg >> 16) & 0x3ff; + if (entry->end) + entry->end += 1; } void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv, @@ -3131,7 +3133,7 @@ skl_allocate_pipe_ddb(struct drm_crtc *crtc, } cursor_blocks = skl_cursor_allocation(config); - ddb->cursor[pipe].start = alloc.end - cursor_blocks + 1; + ddb->cursor[pipe].start = alloc.end - cursor_blocks; ddb->cursor[pipe].end = alloc.end; alloc_size -= cursor_blocks; @@ -3165,7 +3167,7 @@ skl_allocate_pipe_ddb(struct drm_crtc *crtc, total_data_rate); ddb->plane[pipe][plane].start = start; - ddb->plane[pipe][plane].end = start + plane_blocks - 1; + ddb->plane[pipe][plane].end = start + plane_blocks; start += plane_blocks; } @@ -3453,6 +3455,15 @@ static void skl_compute_wm_results(struct drm_device *dev, r->wm_linetime[pipe] = p_wm->linetime; } +static void skl_ddb_entry_write(struct drm_i915_private *dev_priv, uint32_t reg, + const struct skl_ddb_entry *entry) +{ + if (entry->end) + I915_WRITE(reg, (entry->end - 1) << 16 | entry->start); + else + I915_WRITE(reg, 0); +} + static void skl_write_wm_values(struct drm_i915_private *dev_priv, const struct skl_wm_values *new) { @@ -3480,13 +3491,12 @@ static void skl_write_wm_values(struct drm_i915_private *dev_priv, I915_WRITE(CUR_WM_TRANS(pipe), new->cursor_trans[pipe]); for (i = 0; i < intel_num_planes(crtc); i++) - I915_WRITE(PLANE_BUF_CFG(pipe, i), - new->ddb.plane[pipe][i].end << 16 | - new->ddb.plane[pipe][i].start); + skl_ddb_entry_write(dev_priv, + PLANE_BUF_CFG(pipe, i), + &new->ddb.plane[pipe][i]); - I915_WRITE(CUR_BUF_CFG(pipe), - new->ddb.cursor[pipe].end << 16 | - new->ddb.cursor[pipe].start); + skl_ddb_entry_write(dev_priv, CUR_BUF_CFG(pipe), + &new->ddb.cursor[pipe]); } } }