From patchwork Thu Nov 6 01:31:34 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tom.O'Rourke@intel.com X-Patchwork-Id: 5238691 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 13BD1C11AC for ; Thu, 6 Nov 2014 01:30:58 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 3631B2017A for ; Thu, 6 Nov 2014 01:30:57 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 5232920172 for ; Thu, 6 Nov 2014 01:30:56 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id A35D66E786; Wed, 5 Nov 2014 17:30:55 -0800 (PST) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by gabe.freedesktop.org (Postfix) with ESMTP id 1ACC96EA1D for ; Wed, 5 Nov 2014 17:30:54 -0800 (PST) Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by fmsmga103.fm.intel.com with ESMTP; 05 Nov 2014 17:24:36 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="4.97,862,1389772800"; d="scan'208";a="412155128" Received: from torourke-desk.ra.intel.com (HELO localhost.localdomain) ([10.10.34.83]) by FMSMGA003.fm.intel.com with ESMTP; 05 Nov 2014 17:22:21 -0800 From: Tom.O'Rourke@intel.com To: intel-gfx@lists.freedesktop.org Date: Wed, 5 Nov 2014 17:31:34 -0800 Message-Id: <1415237495-89576-2-git-send-email-Tom.O'Rourke@intel.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1415237495-89576-1-git-send-email-Tom.O'Rourke@intel.com> References: <1415237495-89576-1-git-send-email-Tom.O'Rourke@intel.com> Subject: [Intel-gfx] [PATCH 1/2] drm/i915: Use efficient frequency for HSW/BDW X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.2 required=5.0 tests=APOSTROPHE_FROM,BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Tom O'Rourke Updated gen6|8_enable_rps() for Haswell and Broadwell to use the efficient frequency read from pcode. Added hsw_use_efficient_freq() to read efficient frequency (aka RPe) from pcode. The efficiency is based on the frequency/power ratio (MHz/W); this is considering GT power and not package power. The efficent frequency is the highest frequency for which the frequency/power ratio is within some threshold of the highest frequency/power ratio. Also set the min_freq_softlimit to the efficient frequency. A fixed decrease in frequency results in smaller decrease in power at frequencies less than RPe than at frequencies above RPe. Signed-off-by: Tom O'Rourke --- drivers/gpu/drm/i915/i915_reg.h | 1 + drivers/gpu/drm/i915/intel_pm.c | 22 ++++++++++++++++++++++ 2 files changed, 23 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index d43fa0e..6fbfdec 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -6010,6 +6010,7 @@ enum punit_power_well { #define GEN6_ENCODE_RC6_VID(mv) (((mv) - 245) / 5) #define GEN6_DECODE_RC6_VID(vids) (((vids) * 5) + 245) #define DISPLAY_IPS_CONTROL 0x19 +#define HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL 0x1A #define GEN6_PCODE_DATA 0x138128 #define GEN6_PCODE_FREQ_IA_RATIO_SHIFT 8 #define GEN6_PCODE_FREQ_RING_RATIO_SHIFT 16 diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 300d7e5..e4347d9 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -4706,6 +4706,18 @@ static void parse_rp_state_cap(struct drm_i915_private *dev_priv, u32 rp_state_c dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq; } +static void hsw_use_efficient_freq(struct drm_i915_private *dev_priv) +{ + u32 ddcc_status = 0; + int ret; + + ret = sandybridge_pcode_read(dev_priv, + HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL, + &ddcc_status); + if (0 == ret) + dev_priv->rps.efficient_freq = (ddcc_status >> 8) & 0xff; +} + static void gen9_enable_rps(struct drm_device *dev) { struct drm_i915_private *dev_priv = dev->dev_private; @@ -4765,6 +4777,11 @@ static void gen8_enable_rps(struct drm_device *dev) rp_state_cap = I915_READ(GEN6_RP_STATE_CAP); parse_rp_state_cap(dev_priv, rp_state_cap); + if (IS_BROADWELL(dev)) { + hsw_use_efficient_freq(dev_priv); + dev_priv->rps.min_freq_softlimit = dev_priv->rps.efficient_freq; + } + /* 2b: Program RC6 thresholds.*/ I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16); I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */ @@ -4860,6 +4877,11 @@ static void gen6_enable_rps(struct drm_device *dev) parse_rp_state_cap(dev_priv, rp_state_cap); + if (IS_HASWELL(dev)) { + hsw_use_efficient_freq(dev_priv); + dev_priv->rps.min_freq_softlimit = dev_priv->rps.efficient_freq; + } + /* disable the counters and set deterministic thresholds */ I915_WRITE(GEN6_RC_CONTROL, 0);