From patchwork Mon Nov 10 14:56:50 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Bragg X-Patchwork-Id: 5266671 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 133C9C11AC for ; Mon, 10 Nov 2014 14:57:32 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 3E49D20179 for ; Mon, 10 Nov 2014 14:57:31 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 4DA1B20173 for ; Mon, 10 Nov 2014 14:57:30 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id BB5366F736; Mon, 10 Nov 2014 06:57:29 -0800 (PST) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-wg0-f48.google.com (mail-wg0-f48.google.com [74.125.82.48]) by gabe.freedesktop.org (Postfix) with ESMTP id 036C2882C2 for ; Mon, 10 Nov 2014 06:57:28 -0800 (PST) Received: by mail-wg0-f48.google.com with SMTP id m15so9094274wgh.7 for ; Mon, 10 Nov 2014 06:57:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=em/FFB6wgyTS/hvXUaZvfatF3BizPqkTeciXGZWBB8Q=; b=Gl8sNbjP/R6qyzEBrEm0wtJAMY/n+KqqU9bW3GrkIYX36pm4uXhj7FLk8HuNgGrtYl Ey4k33y4aNzgPCkdG/vkBi8tWkDxp6NdezptWfhU/MvWNcY+LRuWnY72YR+Ks6YPAuDu hSuu8VjlZH6TM4vVv4VRgZqsO22tp3ZwIpYu7pmN/vQRb25MS0JSKf5yhH3BhdPeuzFB v8QQYTbLtnylB5s5GpE/sAD1MANvLmZOZpckZXS7cAuArdCuISxCacKDvWGjZEOPigIy a8i4nmt6QP89wiTtPnFj30+qLqDZh6lLJedbR93hSDHpglxTZ6HKS+1p36v630+GT7qX qLVw== X-Received: by 10.194.175.67 with SMTP id by3mr43239033wjc.32.1415631442531; Mon, 10 Nov 2014 06:57:22 -0800 (PST) Received: from sixbynine.org (host-80-43-156-179.as13285.net. [80.43.156.179]) by mx.google.com with ESMTPSA id ex2sm13699203wib.19.2014.11.10.06.57.21 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 10 Nov 2014 06:57:21 -0800 (PST) From: Robert Bragg To: intel-gfx@lists.freedesktop.org Date: Mon, 10 Nov 2014 14:56:50 +0000 Message-Id: <1415631411-11726-4-git-send-email-robert@sixbynine.org> X-Mailer: git-send-email 2.1.3 In-Reply-To: <1415631411-11726-1-git-send-email-robert@sixbynine.org> References: <1415631411-11726-1-git-send-email-robert@sixbynine.org> Subject: [Intel-gfx] [RFC PATCH 3/4] drm/i915: add api to pin/unpin context state X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.6 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED,RP_MATCHES_RCVD,T_DKIM_INVALID,UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This adds i915_gem_context_pin/unpin_state functions so that code outside i915_gem_context.c can pin/unpin a context without duplicating knowledge about the alignment constraints. Signed-off-by: Robert Bragg --- drivers/gpu/drm/i915/i915_drv.h | 4 ++++ drivers/gpu/drm/i915/i915_gem_context.c | 30 +++++++++++++++++++++--------- 2 files changed, 25 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 3212d62..acaf76c 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -2675,6 +2675,10 @@ int i915_gem_context_create_ioctl(struct drm_device *dev, void *data, int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data, struct drm_file *file); +int i915_gem_context_pin_state(struct drm_device *dev, + struct intel_context *ctx); +void i915_gem_context_unpin_state(struct intel_context *ctx); + /* i915_gem_evict.c */ int __must_check i915_gem_evict_something(struct drm_device *dev, struct i915_address_space *vm, diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c index a5221d8..feb1a23 100644 --- a/drivers/gpu/drm/i915/i915_gem_context.c +++ b/drivers/gpu/drm/i915/i915_gem_context.c @@ -132,6 +132,20 @@ static int get_context_size(struct drm_device *dev) return ret; } +int i915_gem_context_pin_state(struct drm_device *dev, + struct intel_context *ctx) +{ + BUG_ON(!mutex_is_locked(&dev->struct_mutex)); + + return i915_gem_obj_ggtt_pin(ctx->legacy_hw_ctx.rcs_state, + get_context_alignment(dev), 0); +} + +void i915_gem_context_unpin_state(struct intel_context *ctx) +{ + i915_gem_object_ggtt_unpin(ctx->legacy_hw_ctx.rcs_state); +} + void i915_gem_context_free(struct kref *ctx_ref) { struct intel_context *ctx = container_of(ctx_ref, @@ -253,8 +267,7 @@ i915_gem_create_context(struct drm_device *dev, * be available. To avoid this we always pin the default * context. */ - ret = i915_gem_obj_ggtt_pin(ctx->legacy_hw_ctx.rcs_state, - get_context_alignment(dev), 0); + ret = i915_gem_context_pin_state(dev, ctx); if (ret) { DRM_DEBUG_DRIVER("Couldn't pin %d\n", ret); goto err_destroy; @@ -278,7 +291,7 @@ i915_gem_create_context(struct drm_device *dev, err_unpin: if (is_global_default_ctx && ctx->legacy_hw_ctx.rcs_state) - i915_gem_object_ggtt_unpin(ctx->legacy_hw_ctx.rcs_state); + i915_gem_context_unpin_state(ctx); err_destroy: i915_gem_context_unreference(ctx); return ERR_PTR(ret); @@ -375,12 +388,12 @@ void i915_gem_context_fini(struct drm_device *dev) if (dev_priv->ring[RCS].last_context == dctx) { /* Fake switch to NULL context */ WARN_ON(dctx->legacy_hw_ctx.rcs_state->active); - i915_gem_object_ggtt_unpin(dctx->legacy_hw_ctx.rcs_state); + i915_gem_context_unpin_state(dctx); i915_gem_context_unreference(dctx); dev_priv->ring[RCS].last_context = NULL; } - i915_gem_object_ggtt_unpin(dctx->legacy_hw_ctx.rcs_state); + i915_gem_context_unpin_state(dctx); } for (i = 0; i < I915_NUM_RINGS; i++) { @@ -534,8 +547,7 @@ static int do_switch(struct intel_engine_cs *ring, /* Trying to pin first makes error handling easier. */ if (ring == &dev_priv->ring[RCS]) { - ret = i915_gem_obj_ggtt_pin(to->legacy_hw_ctx.rcs_state, - get_context_alignment(ring->dev), 0); + ret = i915_gem_context_pin_state(ring->dev, to); if (ret) return ret; } @@ -616,7 +628,7 @@ static int do_switch(struct intel_engine_cs *ring, BUG_ON(from->legacy_hw_ctx.rcs_state->ring != ring); /* obj is kept alive until the next request by its active ref */ - i915_gem_object_ggtt_unpin(from->legacy_hw_ctx.rcs_state); + i915_gem_context_unpin_state(from); i915_gem_context_unreference(from); } @@ -643,7 +655,7 @@ done: unpin_out: if (ring->id == RCS) - i915_gem_object_ggtt_unpin(to->legacy_hw_ctx.rcs_state); + i915_gem_context_unpin_state(to); return ret; }