diff mbox

drm/i915: Use correct pipe config to update pll dividers. V2

Message ID 1415726958-32186-1-git-send-email-bob.j.paauwe@intel.com (mailing list archive)
State New, archived
Headers show

Commit Message

Paauwe, Bob J Nov. 11, 2014, 5:29 p.m. UTC 
Use the new pipe config values to calculate the updated pll dividers.

This regression was introduced in

commit 0dbdf89f27b17ae1eceed6782c2917f74cbb5d59
Author: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
Date:   Wed Oct 29 11:32:33 2014 +0200

    drm/i915: Add infrastructure for choosing DPLLs before disabling crtcs

	and

	commit 00d958817dd3daaa452c221387ddaf23d1e4c06f
	Author: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
	Date:   Wed Oct 29 11:32:36 2014 +0200

	    drm/i915: Covert remaining platforms to choose DPLLS before disabling CRTCs

v2: Use intel_pipe_will_have_type() to look at new configuration - Ander

Signed-off-by: Bob Paauwe <bob.j.paauwe@intel.com>
CC: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

Comments

Jesse Barnes Nov. 11, 2014, 6:34 p.m. UTC | #1 
On Tue, 11 Nov 2014 09:29:18 -0800
Bob Paauwe <bob.j.paauwe@intel.com> wrote:

> Use the new pipe config values to calculate the updated pll dividers.
> 
> This regression was introduced in
> 
> commit 0dbdf89f27b17ae1eceed6782c2917f74cbb5d59
> Author: Ander Conselvan de Oliveira
> <ander.conselvan.de.oliveira@intel.com> Date:   Wed Oct 29 11:32:33
> 2014 +0200
> 
>     drm/i915: Add infrastructure for choosing DPLLs before disabling
> crtcs
> 
> 	and
> 
> 	commit 00d958817dd3daaa452c221387ddaf23d1e4c06f
> 	Author: Ander Conselvan de Oliveira
> <ander.conselvan.de.oliveira@intel.com> Date:   Wed Oct 29 11:32:36
> 2014 +0200
> 
> 	    drm/i915: Covert remaining platforms to choose DPLLS
> before disabling CRTCs
> 
> v2: Use intel_pipe_will_have_type() to look at new configuration -
> Ander
> 
> Signed-off-by: Bob Paauwe <bob.j.paauwe@intel.com>
> CC: Ander Conselvan de Oliveira
> <ander.conselvan.de.oliveira@intel.com> ---
>  drivers/gpu/drm/i915/intel_display.c | 12 ++++++------
>  1 file changed, 6 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c index ff071a7..667d72a 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -5730,24 +5730,24 @@ static void i9xx_update_pll_dividers(struct
> intel_crtc *crtc, u32 fp, fp2 = 0;
>  
>  	if (IS_PINEVIEW(dev)) {
> -		fp = pnv_dpll_compute_fp(&crtc->config.dpll);
> +		fp = pnv_dpll_compute_fp(&crtc->new_config->dpll);
>  		if (reduced_clock)
>  			fp2 = pnv_dpll_compute_fp(reduced_clock);
>  	} else {
> -		fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
> +		fp = i9xx_dpll_compute_fp(&crtc->new_config->dpll);
>  		if (reduced_clock)
>  			fp2 = i9xx_dpll_compute_fp(reduced_clock);
>  	}
>  
> -	crtc->config.dpll_hw_state.fp0 = fp;
> +	crtc->new_config->dpll_hw_state.fp0 = fp;
>  
>  	crtc->lowfreq_avail = false;
> -	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
> +	if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
>  	    reduced_clock && i915.powersave) {
> -		crtc->config.dpll_hw_state.fp1 = fp2;
> +		crtc->new_config->dpll_hw_state.fp1 = fp2;
>  		crtc->lowfreq_avail = true;
>  	} else {
> -		crtc->config.dpll_hw_state.fp1 = fp;
> +		crtc->new_config->dpll_hw_state.fp1 = fp;
>  	}
>  }
>  

Fixes things on my 945 here.  Thanks.

Tested-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Daniel Vetter Nov. 12, 2014, 9:23 a.m. UTC | #2 
On Tue, Nov 11, 2014 at 10:34:15AM -0800, Jesse Barnes wrote:
> On Tue, 11 Nov 2014 09:29:18 -0800
> Bob Paauwe <bob.j.paauwe@intel.com> wrote:
> 
> > Use the new pipe config values to calculate the updated pll dividers.
> > 
> > This regression was introduced in
> > 
> > commit 0dbdf89f27b17ae1eceed6782c2917f74cbb5d59
> > Author: Ander Conselvan de Oliveira
> > <ander.conselvan.de.oliveira@intel.com> Date:   Wed Oct 29 11:32:33
> > 2014 +0200
> > 
> >     drm/i915: Add infrastructure for choosing DPLLs before disabling
> > crtcs
> > 
> > 	and
> > 
> > 	commit 00d958817dd3daaa452c221387ddaf23d1e4c06f
> > 	Author: Ander Conselvan de Oliveira
> > <ander.conselvan.de.oliveira@intel.com> Date:   Wed Oct 29 11:32:36
> > 2014 +0200
> > 
> > 	    drm/i915: Covert remaining platforms to choose DPLLS
> > before disabling CRTCs
> > 
> > v2: Use intel_pipe_will_have_type() to look at new configuration -
> > Ander
> > 
> > Signed-off-by: Bob Paauwe <bob.j.paauwe@intel.com>
> > CC: Ander Conselvan de Oliveira
> > <ander.conselvan.de.oliveira@intel.com> ---

Queued for -next, thanks for the patch.
-Daniel

> >  drivers/gpu/drm/i915/intel_display.c | 12 ++++++------
> >  1 file changed, 6 insertions(+), 6 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_display.c
> > b/drivers/gpu/drm/i915/intel_display.c index ff071a7..667d72a 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -5730,24 +5730,24 @@ static void i9xx_update_pll_dividers(struct
> > intel_crtc *crtc, u32 fp, fp2 = 0;
> >  
> >  	if (IS_PINEVIEW(dev)) {
> > -		fp = pnv_dpll_compute_fp(&crtc->config.dpll);
> > +		fp = pnv_dpll_compute_fp(&crtc->new_config->dpll);
> >  		if (reduced_clock)
> >  			fp2 = pnv_dpll_compute_fp(reduced_clock);
> >  	} else {
> > -		fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
> > +		fp = i9xx_dpll_compute_fp(&crtc->new_config->dpll);
> >  		if (reduced_clock)
> >  			fp2 = i9xx_dpll_compute_fp(reduced_clock);
> >  	}
> >  
> > -	crtc->config.dpll_hw_state.fp0 = fp;
> > +	crtc->new_config->dpll_hw_state.fp0 = fp;
> >  
> >  	crtc->lowfreq_avail = false;
> > -	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
> > +	if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
> >  	    reduced_clock && i915.powersave) {
> > -		crtc->config.dpll_hw_state.fp1 = fp2;
> > +		crtc->new_config->dpll_hw_state.fp1 = fp2;
> >  		crtc->lowfreq_avail = true;
> >  	} else {
> > -		crtc->config.dpll_hw_state.fp1 = fp;
> > +		crtc->new_config->dpll_hw_state.fp1 = fp;
> >  	}
> >  }
> >  
> 
> Fixes things on my 945 here.  Thanks.
> 
> Tested-by: Jesse Barnes <jbarnes@virtuousgeek.org>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Shuang He Nov. 12, 2014, 2:08 p.m. UTC | #3 
Tested-By: PRC QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com)
-------------------------------------Summary-------------------------------------
Platform: baseline_drm_intel_nightly_pass_rate->patch_applied_pass_rate
BYT: pass/total=247/348->276/348
PNV: pass/total=326/328->327/328
ILK: pass/total=329/330->330/330
IVB: pass/total=544/546->544/546
SNB: pass/total=384/384->383/384
HSW: pass/total=583/588->586/588
BDW: pass/total=435/435->433/435
-------------------------------------Detailed-------------------------------------
test_platform: test_suite, test_case, result_with_drm_intel_nightly(count, machine_id...)...->result_with_patch_applied(count, machine_id)...
BYT: Intel_gpu_tools, igt_drv_hangman_error-state-basic, BLACKLIST(1, M31)PASS(24, M31M36M29M38) -> PASS(4, M29)
BYT: Intel_gpu_tools, igt_drv_hangman_error-state-capture-blt, BLACKLIST(1, M31)PASS(24, M31M36M29M38) -> PASS(4, M29)
BYT: Intel_gpu_tools, igt_drv_hangman_error-state-capture-bsd, BLACKLIST(1, M31)PASS(24, M31M36M29M38) -> PASS(4, M29)
BYT: Intel_gpu_tools, igt_drv_hangman_error-state-capture-render, BLACKLIST(1, M31)PASS(24, M31M36M29M38) -> PASS(4, M29)
BYT: Intel_gpu_tools, igt_drv_hangman_error-state-debugfs-entry, BLACKLIST(1, M31)PASS(24, M31M36M29M38) -> PASS(4, M29)
BYT: Intel_gpu_tools, igt_drv_hangman_error-state-sysfs-entry, BLACKLIST(1, M31)PASS(24, M31M36M29M38) -> PASS(4, M29)
BYT: Intel_gpu_tools, igt_gem_bad_reloc_negative-reloc-lut, NSPT(1, M38)PASS(15, M31M29M38) -> NSPT(1, M29)PASS(3, M29)
BYT: Intel_gpu_tools, igt_gem_reset_stats_ban-ctx-render, BLACKLIST(1, M31)PASS(24, M31M36M29M38) -> PASS(4, M29)
BYT: Intel_gpu_tools, igt_gem_reset_stats_ban-render, BLACKLIST(1, M31)PASS(24, M31M36M29M38) -> PASS(4, M29)
BYT: Intel_gpu_tools, igt_gem_reset_stats_close-pending-blt, BLACKLIST(1, M31)DMESG_WARN(11, M31M36M29)PASS(13, M31M36M38) -> DMESG_WARN(2, M29)PASS(2, M29)
BYT: Intel_gpu_tools, igt_gem_reset_stats_close-pending-bsd, BLACKLIST(1, M31)DMESG_WARN(9, M36M29M31)PASS(15, M31M29M38M36) -> DMESG_WARN(1, M29)PASS(3, M29)
BYT: Intel_gpu_tools, igt_gem_reset_stats_close-pending-ctx-render, BLACKLIST(1, M31)PASS(24, M31M36M29M38) -> PASS(4, M29)
BYT: Intel_gpu_tools, igt_gem_reset_stats_close-pending-fork-blt, BLACKLIST(1, M31)DMESG_WARN(11, M31M36M29)PASS(13, M31M36M29M38) -> PASS(4, M29)
BYT: Intel_gpu_tools, igt_gem_reset_stats_close-pending-fork-bsd, BLACKLIST(1, M31)DMESG_WARN(12, M31M36M29)PASS(12, M31M36M29M38) -> DMESG_WARN(2, M29)PASS(2, M29)
BYT: Intel_gpu_tools, igt_gem_reset_stats_close-pending-fork-render, BLACKLIST(1, M31)PASS(24, M31M36M29M38) -> PASS(4, M29)
BYT: Intel_gpu_tools, igt_gem_reset_stats_close-pending-fork-reverse-blt, BLACKLIST(1, M31)PASS(24, M31M36M29M38) -> PASS(4, M29)
BYT: Intel_gpu_tools, igt_gem_reset_stats_close-pending-fork-reverse-bsd, BLACKLIST(1, M31)PASS(24, M31M36M29M38) -> PASS(4, M29)
BYT: Intel_gpu_tools, igt_gem_reset_stats_close-pending-fork-reverse-render, BLACKLIST(1, M31)PASS(24, M31M36M29M38) -> PASS(4, M29)
BYT: Intel_gpu_tools, igt_gem_reset_stats_close-pending-render, BLACKLIST(1, M31)PASS(24, M31M36M29M38) -> PASS(4, M29)
BYT: Intel_gpu_tools, igt_gem_reset_stats_params, BLACKLIST(1, M31)PASS(24, M31M36M29M38) -> PASS(4, M29)
BYT: Intel_gpu_tools, igt_gem_reset_stats_params-ctx-render, BLACKLIST(1, M31)PASS(24, M31M36M29M38) -> PASS(4, M29)
BYT: Intel_gpu_tools, igt_gem_reset_stats_reset-count-blt, BLACKLIST(1, M31)DMESG_WARN(16, M31M36M29)PASS(8, M29M38M36) -> DMESG_WARN(3, M29)PASS(1, M29)
BYT: Intel_gpu_tools, igt_gem_reset_stats_reset-count-bsd, BLACKLIST(1, M31)DMESG_WARN(14, M31M36M29)PASS(10, M36M38M29) -> DMESG_WARN(2, M29)PASS(2, M29)
BYT: Intel_gpu_tools, igt_gem_reset_stats_reset-count-ctx-render, BLACKLIST(1, M31)PASS(24, M31M36M29M38) -> PASS(4, M29)
BYT: Intel_gpu_tools, igt_gem_reset_stats_reset-count-render, BLACKLIST(1, M31)PASS(24, M31M36M29M38) -> PASS(4, M29)
BYT: Intel_gpu_tools, igt_gem_reset_stats_reset-stats-blt, BLACKLIST(1, M31)DMESG_WARN(8, M36M29M31)PASS(16, M31M36M29M38) -> PASS(4, M29)
BYT: Intel_gpu_tools, igt_gem_reset_stats_reset-stats-bsd, BLACKLIST(1, M31)DMESG_WARN(9, M36M29M31)PASS(15, M31M36M29M38) -> DMESG_WARN(1, M29)PASS(3, M29)
BYT: Intel_gpu_tools, igt_gem_reset_stats_reset-stats-ctx-render, BLACKLIST(1, M31)PASS(24, M31M36M29M38) -> PASS(4, M29)
BYT: Intel_gpu_tools, igt_gem_reset_stats_reset-stats-render, BLACKLIST(1, M31)PASS(24, M31M36M29M38) -> PASS(4, M29)
BYT: Intel_gpu_tools, igt_gem_reset_stats_unrelated-ctx-render, BLACKLIST(1, M31)PASS(24, M31M36M29M38) -> PASS(4, M29)
BYT: Intel_gpu_tools, igt_drv_hangman_ring-stop-sysfs-entry, BLACKLIST(1, M31)PASS(24, M31M36M29M38) -> PASS(4, M29)
PNV: Intel_gpu_tools, igt_kms_setmode_invalid-clone-exclusive-crtc, DMESG_WARN(1, M25)PASS(6, M24) -> DMESG_WARN(3, M24)PASS(1, M24)
PNV: Intel_gpu_tools, igt_kms_setmode_invalid-clone-single-crtc, DMESG_WARN(1, M25)TIMEOUT(15, M7M25M24M23)PASS(3, M24) -> DMESG_WARN(3, M24)TIMEOUT(1, M24)
ILK: Intel_gpu_tools, igt_kms_flip_flip-vs-modeset-interruptible, DMESG_WARN(2, M26)PASS(26, M37M26M6) -> PASS(4, M37)
IVB: Intel_gpu_tools, igt_kms_plane_plane-position-covered-pipe-A-plane-1, TIMEOUT(1, M34)PASS(27, M21M4M34) -> PASS(4, M4)
IVB: Intel_gpu_tools, igt_kms_setmode_invalid-clone-single-crtc, TIMEOUT(15, M34M21M4)PASS(1, M34) -> TIMEOUT(1, M4)PASS(3, M4)
SNB: Intel_gpu_tools, igt_kms_setmode_invalid-clone-single-crtc, TIMEOUT(3, M35)PASS(1, M35) -> TIMEOUT(1, M35)PASS(3, M35)
HSW: Intel_gpu_tools, igt_kms_setmode_invalid-clone-single-crtc, PASS(1, M40) -> TIMEOUT(1, M20)PASS(3, M20)
HSW: Intel_gpu_tools, igt_pm_rpm_legacy-planes, TIMEOUT(1, M40) -> TIMEOUT(3, M20)PASS(1, M20)
HSW: Intel_gpu_tools, igt_pm_rpm_legacy-planes-dpms, TIMEOUT(1, M40) -> TIMEOUT(3, M20)PASS(1, M20)
HSW: Intel_gpu_tools, igt_pm_rpm_universal-planes, TIMEOUT(1, M40) -> TIMEOUT(1, M20)PASS(1, M20)
HSW: Intel_gpu_tools, igt_pm_rpm_universal-planes-dpms, TIMEOUT(1, M40) -> PASS(1, M20)
BDW: Intel_gpu_tools, igt_kms_setmode_invalid-clone-single-crtc, TIMEOUT(15, M28M42M30)PASS(1, M42) -> TIMEOUT(1, M30)PASS(3, M30)
BDW: Intel_gpu_tools, igt_gem_reset_stats_ban-bsd, PASS(31, M42M30M28) -> DMESG_WARN(1, M30)PASS(3, M30)
diff mbox

Patch

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index ff071a7..667d72a 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5730,24 +5730,24 @@  static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
 	u32 fp, fp2 = 0;
 
 	if (IS_PINEVIEW(dev)) {
-		fp = pnv_dpll_compute_fp(&crtc->config.dpll);
+		fp = pnv_dpll_compute_fp(&crtc->new_config->dpll);
 		if (reduced_clock)
 			fp2 = pnv_dpll_compute_fp(reduced_clock);
 	} else {
-		fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
+		fp = i9xx_dpll_compute_fp(&crtc->new_config->dpll);
 		if (reduced_clock)
 			fp2 = i9xx_dpll_compute_fp(reduced_clock);
 	}
 
-	crtc->config.dpll_hw_state.fp0 = fp;
+	crtc->new_config->dpll_hw_state.fp0 = fp;
 
 	crtc->lowfreq_avail = false;
-	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
+	if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
 	    reduced_clock && i915.powersave) {
-		crtc->config.dpll_hw_state.fp1 = fp2;
+		crtc->new_config->dpll_hw_state.fp1 = fp2;
 		crtc->lowfreq_avail = true;
 	} else {
-		crtc->config.dpll_hw_state.fp1 = fp;
+		crtc->new_config->dpll_hw_state.fp1 = fp;
 	}
 }