| Message ID | 1415933410-23451-1-git-send-email-Tom.O'Rourke@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Thu, Nov 13, 2014 at 06:50:10PM -0800, Tom.O'Rourke@intel.com wrote: > From: Tom O'Rourke <Tom.O'Rourke@intel.com> > > In sandybridge_pcode_read and sandybridge_pcode_write, > extend the mbox parameter from u8 to u32. > > On Haswell and Sandybridge, bits 7:0 encode the mailbox > command and bits 28:8 are used for address control for > specific commands. > > Based on suggestion from Ville Syrjälä. > > Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com> Not sure what we're going to do with this, but the spec does allow passing some stuff in the high bits, so Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > --- > drivers/gpu/drm/i915/i915_drv.h | 4 ++-- > drivers/gpu/drm/i915/intel_pm.c | 4 ++-- > 2 files changed, 4 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h > index 3f3035c..4dea835 100644 > --- a/drivers/gpu/drm/i915/i915_drv.h > +++ b/drivers/gpu/drm/i915/i915_drv.h > @@ -2954,8 +2954,8 @@ void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv, int fw_engine); > void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv, int fw_engine); > void assert_force_wake_inactive(struct drm_i915_private *dev_priv); > > -int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val); > -int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val); > +int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val); > +int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val); > > /* intel_sideband.c */ > u32 vlv_punit_read(struct drm_i915_private *dev_priv, u8 addr); > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > index 9e87265..21faa92 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -7154,7 +7154,7 @@ void intel_init_pm(struct drm_device *dev) > } > } > > -int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val) > +int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val) > { > WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); > > @@ -7180,7 +7180,7 @@ int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val) > return 0; > } > > -int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val) > +int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val) > { > WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); > > -- > 1.7.9.5 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
On Tue, Nov 18, 2014 at 09:24:26PM +0200, Ville Syrjälä wrote: > On Thu, Nov 13, 2014 at 06:50:10PM -0800, Tom.O'Rourke@intel.com wrote: > > From: Tom O'Rourke <Tom.O'Rourke@intel.com> > > > > In sandybridge_pcode_read and sandybridge_pcode_write, > > extend the mbox parameter from u8 to u32. > > > > On Haswell and Sandybridge, bits 7:0 encode the mailbox > > command and bits 28:8 are used for address control for > > specific commands. > > > > Based on suggestion from Ville Syrjälä. > > > > Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com> > > Not sure what we're going to do with this, but the spec does allow > passing some stuff in the high bits, so > > Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Queued for -next, thanks for the patch. -Daniel
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 3f3035c..4dea835 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -2954,8 +2954,8 @@ void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv, int fw_engine); void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv, int fw_engine); void assert_force_wake_inactive(struct drm_i915_private *dev_priv); -int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val); -int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val); +int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val); +int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val); /* intel_sideband.c */ u32 vlv_punit_read(struct drm_i915_private *dev_priv, u8 addr); diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 9e87265..21faa92 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -7154,7 +7154,7 @@ void intel_init_pm(struct drm_device *dev) } } -int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val) +int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val) { WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); @@ -7180,7 +7180,7 @@ int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val) return 0; } -int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val) +int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val) { WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));