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[5/5] drm/i915: Introduce intel_prepare_cursor_plane()

Message ID 1416363529-2034-6-git-send-email-matthew.d.roper@intel.com (mailing list archive)
State New, archived
Headers show

Commit Message

Matt Roper Nov. 19, 2014, 2:18 a.m. UTC
Primary and sprite planes have already been refactored to include a
'prepare' step which handles all the commit-time operations that could
fail (i.e., pinning buffers and such).  Refactor the cursor commit in a
similar manner.

For simplicity and consistency with other plane types, we also switch to
using intel_pin_and_fence_fb_obj() to perform our pinning for
non-physical cursors.  This will allow us to more easily migrate the
code into the atomic 'begin' handler in a plane-agnostic manner in a
future patchset.

Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 114 ++++++++++++++---------------------
 1 file changed, 44 insertions(+), 70 deletions(-)

Comments

Shuang He Nov. 19, 2014, 10:32 a.m. UTC | #1
Tested-By: PRC QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com)
-------------------------------------Summary-------------------------------------
Platform          Delta          drm-intel-nightly          Series Applied
PNV                                  369/369              369/369
ILK                 -1              403/403              402/403
SNB                 -1              459/459              458/459
IVB                 -1              535/545              534/545
BYT                                  290/290              290/290
HSW                 -1              610/610              609/610
BDW                                  451/451              451/451
-------------------------------------Detailed-------------------------------------
test_platform: test_suite, test_case, result_with_drm_intel_nightly(count, machine_id...)...->result_with_patch_applied(count, machine_id)...
ILK: Intel_gpu_tools, igt_kms_3d, DMESG_WARN(3, M37)PASS(1, M6) -> DMESG_WARN(1, M37)PASS(3, M37)
SNB: Intel_gpu_tools, igt_kms_3d, DMESG_WARN(6, M22M35)PASS(1, M35) -> DMESG_WARN(1, M35)PASS(3, M35)
IVB: Intel_gpu_tools, igt_kms_3d, DMESG_WARN(6, M4M34)PASS(1, M21) -> DMESG_WARN(1, M34)PASS(3, M34)
HSW: Intel_gpu_tools, igt_gem_reset_stats_close-pending-fork-render, PASS(4, M19M40) -> NO_RESULT(1, M40)PASS(3, M40)
diff mbox

Patch

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 3482946..a0247e7 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -11850,19 +11850,51 @@  intel_check_cursor_plane(struct drm_plane *plane,
 }
 
 static int
+intel_prepare_cursor_plane(struct drm_plane *plane,
+			   struct intel_plane_state *state)
+{
+	struct drm_device *dev = plane->dev;
+	struct drm_framebuffer *fb = state->fb;
+	struct intel_crtc *intel_crtc = to_intel_crtc(state->crtc);
+	struct drm_i915_gem_object *obj = intel_fb_obj(fb);
+	struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
+	enum pipe pipe = intel_crtc->pipe;
+	int ret = 0;
+
+	if (old_obj != obj) {
+		/* we only need to pin inside GTT if cursor is non-phy */
+		mutex_lock(&dev->struct_mutex);
+		if (!INTEL_INFO(dev)->cursor_needs_physical) {
+			if (obj)
+				ret = intel_pin_and_fence_fb_obj(plane, fb, NULL);
+			if (ret == 0)
+				i915_gem_track_fb(intel_crtc->cursor_bo, obj,
+						  INTEL_FRONTBUFFER_CURSOR(pipe));
+		} else {
+			int align = IS_I830(dev) ? 16 * 1024 : 256;
+			if (obj)
+				ret = i915_gem_object_attach_phys(obj, align);
+			if (ret)
+				DRM_DEBUG_KMS("failed to attach phys object\n");
+		}
+		mutex_unlock(&dev->struct_mutex);
+	}
+
+	return ret;
+}
+
+static void
 intel_commit_cursor_plane(struct drm_plane *plane,
 			  struct intel_plane_state *state)
 {
 	struct drm_crtc *crtc = state->crtc;
 	struct drm_device *dev = crtc->dev;
-	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 	struct intel_plane *intel_plane = to_intel_plane(plane);
 	struct drm_i915_gem_object *obj = intel_fb_obj(state->fb);
 	enum pipe pipe = intel_crtc->pipe;
 	unsigned old_width;
 	uint32_t addr;
-	int ret;
 
 	crtc->cursor_x = state->orig_dst.x1;
 	crtc->cursor_y = state->orig_dst.y1;
@@ -11880,75 +11912,18 @@  intel_commit_cursor_plane(struct drm_plane *plane,
 	if (intel_crtc->cursor_bo == obj)
 		goto update;
 
-	/* if we want to turn off the cursor ignore width and height */
-	if (!obj) {
-		DRM_DEBUG_KMS("cursor off\n");
+	if (!obj)
 		addr = 0;
-		mutex_lock(&dev->struct_mutex);
-		goto finish;
-	}
-
-	/* we only need to pin inside GTT if cursor is non-phy */
-	mutex_lock(&dev->struct_mutex);
-	if (!INTEL_INFO(dev)->cursor_needs_physical) {
-		unsigned alignment;
-
-		/*
-		 * Global gtt pte registers are special registers which actually
-		 * forward writes to a chunk of system memory. Which means that
-		 * there is no risk that the register values disappear as soon
-		 * as we call intel_runtime_pm_put(), so it is correct to wrap
-		 * only the pin/unpin/fence and not more.
-		 */
-		intel_runtime_pm_get(dev_priv);
-
-		/* Note that the w/a also requires 2 PTE of padding following
-		 * the bo. We currently fill all unused PTE with the shadow
-		 * page and so we should always have valid PTE following the
-		 * cursor preventing the VT-d warning.
-		 */
-		alignment = 0;
-		if (need_vtd_wa(dev))
-			alignment = 64*1024;
-
-		ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
-		if (ret) {
-			DRM_DEBUG_KMS("failed to move cursor bo into the GTT\n");
-			intel_runtime_pm_put(dev_priv);
-			goto fail_locked;
-		}
-
-		ret = i915_gem_object_put_fence(obj);
-		if (ret) {
-			DRM_DEBUG_KMS("failed to release fence for cursor");
-			intel_runtime_pm_put(dev_priv);
-			goto fail_unpin;
-		}
-
+	else if (!INTEL_INFO(dev)->cursor_needs_physical)
 		addr = i915_gem_obj_ggtt_offset(obj);
-
-		intel_runtime_pm_put(dev_priv);
-
-	} else {
-		int align = IS_I830(dev) ? 16 * 1024 : 256;
-		ret = i915_gem_object_attach_phys(obj, align);
-		if (ret) {
-			DRM_DEBUG_KMS("failed to attach phys object\n");
-			goto fail_locked;
-		}
+	else
 		addr = obj->phys_handle->busaddr;
-	}
 
-finish:
 	if (intel_crtc->cursor_bo) {
 		if (!INTEL_INFO(dev)->cursor_needs_physical)
 			i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo);
 	}
 
-	i915_gem_track_fb(intel_crtc->cursor_bo, obj,
-			  INTEL_FRONTBUFFER_CURSOR(pipe));
-	mutex_unlock(&dev->struct_mutex);
-
 	intel_crtc->cursor_addr = addr;
 	intel_crtc->cursor_bo = obj;
 update:
@@ -11964,13 +11939,6 @@  update:
 
 		intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_CURSOR(pipe));
 	}
-
-	return 0;
-fail_unpin:
-	i915_gem_object_unpin_from_display_plane(obj);
-fail_locked:
-	mutex_unlock(&dev->struct_mutex);
-	return ret;
 }
 
 static int
@@ -12011,7 +11979,13 @@  intel_cursor_plane_update(struct drm_plane *plane, struct drm_crtc *crtc,
 	if (ret)
 		return ret;
 
-	return intel_commit_cursor_plane(plane, &state);
+	ret = intel_prepare_cursor_plane(plane, &state);
+	if (ret)
+		return ret;
+
+	intel_commit_cursor_plane(plane, &state);
+
+	return 0;
 }
 
 static const struct drm_plane_funcs intel_cursor_plane_funcs = {